From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09F25C433F5 for ; Wed, 22 Sep 2021 06:54:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEDB561131 for ; Wed, 22 Sep 2021 06:54:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BEDB561131 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ZEud+XraMVPubw0ERFwUxr3sY1a7TrAyigg07IXyruY=; b=gL5kIIJWexxwx4kspDN0SlQ0Nj WUMfs/2NPAS16+A8pLavk09OwYAHKKRjDN/xZ6HzTLDsfiO+6/Mm2cm8/mDgtnt87j5DhUwZXMEbP sLs1SRNoUVL/XamOAG2TYjJX9zwo2ofrSPzZ4lxI6iqR/L/9ufCohHaGUvZxdhBrZB7K5GBcnJ0bE WavAR00VTfZtwlsNiwDRbCUGbZ0qaMnaA9bKA+O8mNrMJPCgDrt9Vi/0Ugpe/XdxbwjxTPd1i9JC1 k2mYEpgDD/Gurzk8JyfEWL4B3uWZFBIhfhIvlNq2wotc6TFU06hSv7LDJeCyQNuTNWVByAVsSWNPE 8iVI5fJg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSw7T-007ALD-Ls; Wed, 22 Sep 2021 06:52:40 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSw1l-0078eH-Cr for linux-arm-kernel@lists.infradead.org; Wed, 22 Sep 2021 06:46:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2B1B113E; Tue, 21 Sep 2021 23:46:41 -0700 (PDT) Received: from [10.163.73.113] (unknown [10.163.73.113]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 732593F40C; Tue, 21 Sep 2021 23:46:37 -0700 (PDT) Subject: Re: [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-3-suzuki.poulose@arm.com> From: Anshuman Khandual Message-ID: <7384656b-2777-d5d5-0c5a-d30ee6dde20a@arm.com> Date: Wed, 22 Sep 2021 12:17:43 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210921134121.2423546-3-suzuki.poulose@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210921_234645_633554_EC15C9D2 X-CRM114-Status: GOOD ( 35.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/21/21 7:11 PM, Suzuki K Poulose wrote: > Add a minimal infrastructure to keep track of the errata > affecting the given TRBE instance. Given that we have > heterogeneous CPUs, we have to manage the list per-TRBE > instance to be able to apply the work around as needed. > > We rely on the arm64 errata framework for the actual > description and the discovery of a given erratum, to > keep the Erratum work around at a central place and > benefit from the code and the advertisement from the > kernel. We use a local mapping of the erratum to > avoid bloating up the individual TRBE structures. > i.e, each arm64 TRBE erratum bit is assigned a new number > within the driver to track. Each trbe instance updates > the list of affected erratum at probe time on the CPU. > This makes sure that we can easily access the list of > errata on a given TRBE instance without much overhead. > > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Leo Yan > Cc: Anshuman Khandual > Signed-off-by: Suzuki K Poulose > --- > Changes since v1: > - Flip the order of args for trbe_has_erratum() > - Move erratum detection further down in the sequence > --- > drivers/hwtracing/coresight/coresight-trbe.c | 49 ++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index e3d73751d568..63f7edd5fd1f 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -16,6 +16,8 @@ > #define pr_fmt(fmt) DRVNAME ": " fmt > > #include > +#include > + > #include "coresight-self-hosted-trace.h" > #include "coresight-trbe.h" > > @@ -65,6 +67,35 @@ struct trbe_buf { > struct trbe_cpudata *cpudata; > }; > > +/* > + * TRBE erratum list > + * > + * We rely on the corresponding cpucaps to be defined for a given > + * TRBE erratum. We map the given cpucap into a TRBE internal number > + * to make the tracking of the errata lean. > + * > + * This helps in : > + * - Not duplicating the detection logic > + * - Streamlined detection of erratum across the system > + * > + * Since the erratum work arounds could be applied individually > + * per TRBE instance, we keep track of the list of errata that > + * affects the given instance of the TRBE. > + */ > +#define TRBE_ERRATA_MAX 0 > + > +static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = { > +}; Hence TRBE_ERRATA_MAX needs to be updated manually here when new TRBE specific erratums get added to the cpucap list. Hence lets add a comment indicating that the TRBE_ERRATA_MAX needs explicit syncing with changes to cpucap list. > + > +/* > + * struct trbe_cpudata: TRBE instance specific data > + * @trbe_flag - TRBE dirty/access flag support > + * @tbre_align - Actual TRBE alignment required for TRBPTR_EL1. > + * @cpu - CPU this TRBE belongs to. > + * @mode - Mode of current operation. (perf/disabled) > + * @drvdata - TRBE specific drvdata > + * @errata - Bit map for the errata on this TRBE. > + */ > struct trbe_cpudata { > bool trbe_flag; > u64 trbe_align; > @@ -72,6 +103,7 @@ struct trbe_cpudata { > enum cs_mode mode; > struct trbe_buf *buf; > struct trbe_drvdata *drvdata; > + DECLARE_BITMAP(errata, TRBE_ERRATA_MAX); > }; > > struct trbe_drvdata { > @@ -84,6 +116,21 @@ struct trbe_drvdata { > struct platform_device *pdev; > }; > > +static void trbe_check_errata(struct trbe_cpudata *cpudata) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(trbe_errata_cpucaps); i++) { > + if (this_cpu_has_cap(trbe_errata_cpucaps[i])) > + set_bit(i, cpudata->errata); > + } > +} > + > +static inline bool trbe_has_erratum(struct trbe_cpudata *cpudata, int i) > +{ > + return (i < TRBE_ERRATA_MAX) && test_bit(i, cpudata->errata); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -926,6 +973,8 @@ static void arm_trbe_probe_cpu(void *info) > pr_err("Unsupported alignment on cpu %d\n", cpu); > goto cpu_clear; > } > + > + trbe_check_errata(cpudata); This could be moved further down just before the 'return' statement. Lets not interrupt cpudata init sequence, rather run all the errata detection right at the end. > cpudata->trbe_flag = get_trbe_flag_update(trbidr); > cpudata->cpu = cpu; > cpudata->drvdata = drvdata; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel