From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47BD8ECAAD1 for ; Wed, 31 Aug 2022 14:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Cc:To:From:Subject:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4xV8oZKc/cbrQskkh+mnw51SB4s54Fzas5SrQ5KHV54=; b=o7ZAKPo8ephxfS HjCuMr5/rK2H0x5W+RzrOQeKe4oR2iyJM+dwk8I3uGczTXRR3OSJRUFz24WWigXfpVj40344DvtaW WMLEtc+3w81rNynjWlHfrVY5Ms/S7madmr7DuGTl45Vs2Z70LJ7u0Vf9t9IWYaI6LmVC5bkU4C651 JKZx75R1BwJgD3KZKJxyKEoxExeiEaycE4P/9Ekk6BnEKjabberFVCxl5YN5DVY1KcrqsEHAURlaq Ib6tcYMoiSnFMwmiwizZu+fSQd9cJMLRJSOpVuiiDgyX9drgcshQxhwYEIDnrQZ7HcB2zDmV/vQ1I pPKWyJT7kEq8BiRSWcnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTPAy-006pt5-N6; Wed, 31 Aug 2022 14:58:44 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTPAu-006pr8-NE for linux-arm-kernel@lists.infradead.org; Wed, 31 Aug 2022 14:58:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1661957920; x=1693493920; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6QsTRvxqh42QrKAqaGkKTr8ea/gZV5ndpZDKx4HwhiY=; b=GzuSYOZZHKZpCtuaRLloIIANNnwgkR4ejjw+T/UN23YkkzYOTrnDCdCj dFF13zGjmkWCYuPpEh7Ojvr8UWTwvxnHWU2eBl5hczkbg5SiA880y4RCh Q+WaYcN5BYyOMIB5mK6aFD3PflcytTtDzjYdsZ05Kmv9t3LVvxV8V0gEw wpO7lMwuwwhIHHRXekQjlBOvL8zBVFEPJjvRrqp+dr/+nwzpMuY0EdSPM uMvhjLcfCYEEPIg+BQCOjB2g6CwI69CypZCL2o/TKuQsJrF4dwYuuCzog 2RQ0bV3jBNOrpwonSmXoBSr0stSKcLraIMQYn4srqPTSEfXSjMQDhGS2H A==; X-IronPort-AV: E=Sophos;i="5.93,278,1654552800"; d="scan'208";a="25914795" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 31 Aug 2022 16:58:33 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Wed, 31 Aug 2022 16:58:33 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Wed, 31 Aug 2022 16:58:33 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1661957913; x=1693493913; h=from:to:cc:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding:subject; bh=6QsTRvxqh42QrKAqaGkKTr8ea/gZV5ndpZDKx4HwhiY=; b=BnsMTziXzARlphT8LN55oF6eN++6dQ/lZJD6YlNbku7Jodju5gvBZzmO ZQ+L+OZvzKTbPNKvji+7YSeVLhdCKr1tG0W4Mjpa+UBO5hFXMSuUQ1fl7 mN1zuCrYCrFeIOfvT+SBdRxaIUlauxgLvmpJ8dRoILL1bQW7oNZw1Ks11 afpcw+NswzpeemC1oo3jUSsZH1q6kLvzjX47mlxrdY07VneOxinP1jJ+E X+FFvIADp+ZHoh15oYkhqmRr9i9HUN8sh//zv7peedzZEhsq9TZfYf8l0 Ix0ww9lM5Vq5NcmaddYZgUb8EiEadHvH8AjVzhIfNFERTHA49fNvxqOiN Q==; X-IronPort-AV: E=Sophos;i="5.93,278,1654552800"; d="scan'208";a="25914794" Subject: Re: Re: [PATCH] arm64: dts: imx8mp: Add SNVS LPGPR Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 31 Aug 2022 16:58:33 +0200 Received: from steina-w.localnet (unknown [10.123.49.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 98379280056; Wed, 31 Aug 2022 16:58:33 +0200 (CEST) From: Alexander Stein To: Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, Fabio Estevam , Marcel Ziswiler , Peng Fan , Rob Herring , Shawn Guo , NXP Linux Team , devicetree@vger.kernel.org Date: Wed, 31 Aug 2022 16:58:31 +0200 Message-ID: <7425574.EvYhyI6sBW@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <95506426-6458-16c9-19c9-03f07aab734a@denx.de> References: <20220823165602.275931-1-marex@denx.de> <11067634.nUPlyArG6x@steina-w> <95506426-6458-16c9-19c9-03f07aab734a@denx.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_075841_185622_9115DAA2 X-CRM114-Status: GOOD ( 20.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marek, Am Mittwoch, 31. August 2022, 16:45:31 CEST schrieb Marek Vasut: > On 8/24/22 07:51, Alexander Stein wrote: > > Hello Marek, > > Hi, > > > Am Dienstag, 23. August 2022, 18:56:02 CEST schrieb Marek Vasut: > >> Add SNVS LPGPR bindings to MX8M Plus, the LPGPR is used to store > >> e.g. boot counter. > > [...] > > >> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > >> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > >> f7adcb2c14880..21689e9e68170 100644 > >> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > >> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > >> @@ -478,6 +478,11 @@ snvs_pwrkey: snvs-powerkey { > >> > >> wakeup-source; > >> status = "disabled"; > >> > >> }; > >> > >> + > >> + snvs_lpgpr: snvs-lpgpr { > >> + compatible = > > > > "fsl,imx8mp-snvs-lpgpr", > > > >> + > > > > "fsl,imx7d-snvs-lpgpr"; > > > >> + }; > >> > >> }; > >> > >> clk: clock-controller@30380000 { > > > > Do you have any information that the i.MX8M Plus actually has the HPLR > > register (at offset 0)? This is used in snvs_lpgpr_write. I can't find it > > in the RM, although GPR_SL is referenced in LPGPRx register description. > It seems the HPLR is only documented in the Security RM (MX8MMSRM, > MX8MPSRM etc), not in the regular RM (MX8MMRM, MX8MPRM etc) . So it > seems the register does exist, including the soft lock bit, it is only > omitted from the plain RM. > > (also, sorry for the delayed reply) Ah, there it is. Nice! Reviewed-by: Alexander Stein _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel