From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mark Brown <broonie@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH 2/5] arm64/sysreg: Convert MDCCINT_EL1 to automatic register generation
Date: Tue, 23 May 2023 13:53:32 +0530 [thread overview]
Message-ID: <742672ff-bb53-46e9-048c-a2201cb0be2f@arm.com> (raw)
In-Reply-To: <20230419-arm64-syreg-gen-v1-2-936cd769cb9e@kernel.org>
On 5/22/23 21:52, Mark Brown wrote:
> Convert MDCCINT_EL1 to automatic register generation as per DDI0616
> 2023-03. No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 7 +++++++
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6505665624d4..4e48bb4dca6a 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -134,7 +134,6 @@
> #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
> #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
>
> -#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
> #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
> #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
> #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index dd5a9c7e310f..1699e87bc0b4 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -48,6 +48,13 @@
> # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
> # item ACCDATA) though it may be more taseful to do something else.
>
> +Sysreg MDCCINT_EL1 2 0 0 2 0
> +Res0 63:31
> +Field 30 RX
> +Field 29 TX
> +Res0 28:0
> +EndSysreg
> +
> Sysreg ID_PFR0_EL1 3 0 0 1 0
> Res0 63:32
> UnsignedEnum 31:28 RAS
>
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next prev parent reply other threads:[~2023-05-23 8:24 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-22 16:22 [PATCH 0/5] b4/sysreg: More conversions to automatic generation Mark Brown
2023-05-22 16:22 ` [PATCH 1/5] arm64/sysreg: Remove some unused sysreg definitions Mark Brown
2023-05-23 8:23 ` Anshuman Khandual
2023-05-23 11:31 ` Shaoqin Huang
2023-05-23 11:40 ` Marc Zyngier
2023-05-22 16:22 ` [PATCH 2/5] arm64/sysreg: Convert MDCCINT_EL1 to automatic register generation Mark Brown
2023-05-23 8:23 ` Anshuman Khandual [this message]
2023-05-23 11:33 ` Shaoqin Huang
2023-05-22 16:22 ` [PATCH 3/5] arm64/sysreg: Convert MDSCR_EL1 " Mark Brown
2023-05-23 11:40 ` Shaoqin Huang
2023-05-22 16:22 ` [PATCH 4/5] arm64/sysreg: Standardise naming of bitfield constants in OSL[AS]R_EL1 Mark Brown
2023-05-23 11:52 ` Shaoqin Huang
2023-05-22 16:22 ` [PATCH 5/5] arm64/sysreg: Convert OSLAR_EL1 to automatic generation Mark Brown
2023-05-23 8:13 ` Oliver Upton
2023-05-23 8:21 ` Anshuman Khandual
2023-05-23 8:39 ` Mark Brown
2023-05-23 11:53 ` Shaoqin Huang
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