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From: Ashish Mhetre <amhetre@nvidia.com>
To: Will Deacon <will@kernel.org>, Jason Gunthorpe <jgg@ziepe.ca>
Cc: robin.murphy@arm.com, joro@8bytes.org, nicolinc@nvidia.com,
	linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v3 3/3] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264
Date: Fri, 5 Jun 2026 20:11:43 +0530	[thread overview]
Message-ID: <743497d9-b5b8-4de1-a1d4-9d2243b57aeb@nvidia.com> (raw)
In-Reply-To: <aiAQ9ApqfTsdweRg@willie-the-truck>



On 6/3/2026 5:03 PM, Will Deacon wrote:
> External email: Use caution opening links or attachments
>
>
> On Tue, Jun 02, 2026 at 10:01:14PM -0300, Jason Gunthorpe wrote:
>> On Tue, Jun 02, 2026 at 09:22:15PM +0100, Will Deacon wrote:
>>>> + /*
>>>> +  * On Tegra264 (see ARM_SMMU_OPT_TLBI_TWICE) re-issue the same
>>>> +  * cmdlist with another CMD_SYNC to satisfy the erratum.
>>>> +  * Callers must ensure the batch carries a uniform opcode class
>>>> +  * so that checking the first command is enough; the iommufd
>>>> +  * VSMMU path enforces this with arm_vsmmu_can_batch_cmd().
>>>> +  */
>>>> + if (!ret && sync && arm_smmu_cmd_needs_tlbi_twice(smmu, &cmds[0]))
>>> Can you move the arm_smmu_cmd_... part to the start of the conjunction,
>>> please? If you make it a static key as I mentioned previously, then
>>> hopefully that should mean everything else is moved out of line.
>>>
>>>> +         ret = __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync);
>>> Sashiko is also unhappy here if n == 0 because we probably shouldn't
>>> be inspecting the command array in that case.
>> That seems like an AI mistake though, we shouldn't actually ever pass
>> in 0 sized batches? 'zero streams' should fail probe, not get into
>> this code, that might be missing but I wouldn't add checks here..
> I was wondering about the case where the first command in a batch is
> unsupported. Can we issue a bare sync in that case?

Seems a valid case. But considering the static branch approach, will
it be fine to add "n != 0" check before arm_smmu_cmd_needs_tlbi_twice() 
? Something like: int ret = __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, 
cmds, n, sync);
if(!n) return ret; if (arm_smmu_erratum_cmd_needs_repeating(smmu, 
&cmds[0]) && !ret && sync) ret = __arm_smmu_cmdq_issue_cmdlist(smmu, 
cmdq, cmds, n, sync);
> Will

Thanks,
Ashish Mhetre


  reply	other threads:[~2026-06-05 14:42 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-01 10:48 [PATCH v3 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Ashish Mhetre
2026-06-01 10:48 ` [PATCH v3 1/3] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Ashish Mhetre
2026-06-02 19:55   ` Will Deacon
2026-06-02 20:08     ` Nicolin Chen
2026-06-02 20:23       ` Will Deacon
2026-06-01 10:48 ` [PATCH v3 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum Ashish Mhetre
2026-06-02 20:13   ` Will Deacon
2026-06-02 20:31     ` Nicolin Chen
2026-06-02 20:59       ` Will Deacon
2026-06-02 21:06         ` Nicolin Chen
2026-06-05 14:05     ` Ashish Mhetre
2026-06-05 14:10       ` Jason Gunthorpe
2026-06-09  7:07         ` Ashish Mhetre
2026-06-01 10:48 ` [PATCH v3 3/3] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264 Ashish Mhetre
2026-06-01 18:37   ` Nicolin Chen
2026-06-02 20:22   ` Will Deacon
2026-06-02 20:35     ` Nicolin Chen
2026-06-03  0:59     ` Jason Gunthorpe
2026-06-03  1:01     ` Jason Gunthorpe
2026-06-03 11:33       ` Will Deacon
2026-06-05 14:41         ` Ashish Mhetre [this message]
2026-06-05 14:12     ` Ashish Mhetre
2026-06-02 16:31 ` [PATCH v3 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Mostafa Saleh
2026-06-02 18:23   ` Jason Gunthorpe

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