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Thu, 19 Dec 2019 06:50:30 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0B732C494B4; Thu, 19 Dec 2019 06:50:28 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 10D61C48B03; Thu, 19 Dec 2019 06:50:28 +0000 (UTC) MIME-Version: 1.0 Date: Thu, 19 Dec 2019 12:20:27 +0530 From: Sai Prakash Ranjan To: Rob Herring Subject: Re: [PATCH 1/2] dt-bindings: edac: Add DT bindings for Kryo EDAC In-Reply-To: <20191218233714.GA30302@bogus> References: <0101016ed57a3259-eee09e9e-e99a-40f1-ab1c-63e58a42615c-000000@us-west-2.amazonses.com> <20191218233714.GA30302@bogus> Message-ID: <7469b239edd4beed3e8fefdf02f10ada@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191218_225033_522725_D6FD32A5 X-CRM114-Status: GOOD ( 15.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Tony Luck , psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, Stephen Boyd , tsoni@codeaurora.org, linux-kernel@vger.kernel.org, Evan Green , Bjorn Andersson , Robert Richter , Andy Gross , Borislav Petkov , James Morse , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, On 2019-12-19 05:07, Rob Herring wrote: > On Thu, Dec 05, 2019 at 09:53:05AM +0000, Sai Prakash Ranjan wrote: >> This adds DT bindings for Kryo EDAC implemented with RAS >> extensions on KRYO{3,4}XX CPU cores for reporting of cache >> errors. >> >> Signed-off-by: Sai Prakash Ranjan >> --- >> .../bindings/edac/qcom-kryo-edac.yaml | 67 >> +++++++++++++++++++ >> 1 file changed, 67 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >> >> diff --git >> a/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >> b/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >> new file mode 100644 >> index 000000000000..1a39429a73b4 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml >> @@ -0,0 +1,67 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/edac/qcom-kryo-edac.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Kryo Error Detection and Correction(EDAC) >> + >> +maintainers: >> + - Sai Prakash Ranjan >> + >> +description: | >> + Kryo EDAC is defined to describe on-chip error detection and >> correction >> + for the Kryo CPU cores which implement RAS extensions. It will >> report >> + all Single Bit Errors and Double Bit Errors found in L1/L2 caches >> in >> + in two registers ERXSTATUS_EL1 and ERXMISC0_EL1. L3-SCU cache >> errors >> + are reported in ERR1STATUS and ERR1MISC0 registers. >> + ERXSTATUS_EL1 - Selected Error Record Primary Status Register, >> EL1 >> + ERXMISC0_EL1 - Selected Error Record Miscellaneous Register 0, >> EL1 >> + ERR1STATUS - Error Record Primary Status Register >> + ERR1MISC0 - Error Record Miscellaneous Register 0 >> + Current implementation of Kryo ECC(Error Correcting Code) mechanism >> is >> + based on interrupts. >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,kryo-edac >> + >> + interrupts: >> + minItems: 1 >> + maxItems: 4 >> + items: >> + - description: l1-l2 cache faultirq interrupt >> + - description: l1-l2 cache errirq interrupt >> + - description: l3-scu cache errirq interrupt >> + - description: l3-scu cache faultirq interrupt >> + >> + interrupt-names: >> + minItems: 1 >> + maxItems: 4 > > You are saying only these combinations are valid: > > l1-l2-faultirq > > l1-l2-faultirq > l1-l2-errirq > > l1-l2-faultirq > l1-l2-errirq > l3-scu-errirq > > l1-l2-faultirq > l1-l2-errirq > l3-scu-errirq > l3-scu-faultirq > > Is that your intent? > No, I want any combination of interrupts to be valid with atleast one interrupt as mandatory. I thought specifying minItems as 1 and maxItems as 4 will take care of this, am I doing something wrong? Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel