From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F12ACA9ED2 for ; Mon, 4 Nov 2019 09:18:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4ED3F222D4 for ; Mon, 4 Nov 2019 09:18:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fqJsDbbJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4ED3F222D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Date:Message-ID:To:Subject :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=IFokTS6PZU2i+h3oMQWYUJtSRu9T3w7yeOtErmqu4nY=; b=fqJsDbbJQGwJ/v 0wBut4HMWUKUaeSqVhJzTy3M/NM6+Y9qEvRN3ua4uraNraz8D4c1BCMdmVFmrc1LdE+YA/JLKNXQC TrN3qDjsn6WSbKFDRv1wro9wB8Q6+qALIiOdKs68rwiWxX6gu+7LTyIpJfdK4i9n23wbMqJPsEXQd KAA7UYOdYSZUNlMwQ0vsbbaK15mGwwwwhu8yPsjTbLHVbFooq4j4GNlg0rIcgXpIVRly+oIhkLDA4 6SzxWt9tirziHtX997qlcxmkIh8PnkrWKqNUblMXFcM7UQRdvqcjhHPXOUifAqaLZr+YJhttkEa3Z HrkqtMXKOG8eA/JwZ+Zg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iRYV8-0007Df-RD; Mon, 04 Nov 2019 09:18:18 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iRYV4-0007Cd-Pq for linux-arm-kernel@lists.infradead.org; Mon, 04 Nov 2019 09:18:16 +0000 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id E9CEA40EDF38CDC4749A; Mon, 4 Nov 2019 17:18:09 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Mon, 4 Nov 2019 17:18:00 +0800 From: Shaokun Zhang Subject: [RFC] About perf-mem command support on arm64 platform To: , Message-ID: <74f8ddb5-13cc-5dce-82a6-ca8bd02f8175@hisilicon.com> Date: Mon, 4 Nov 2019 17:18:00 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191104_011815_013492_E6E88F78 X-CRM114-Status: GOOD ( 10.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Jiri Olsa , john.garry@huawei.com, Arnaldo Carvalho de Melo , liuqi115@hisilicon.com, huangdaode@hisilicon.com, Jonathan Cameron , Will Deacon Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi all, perf-mem is used to profile memory access which has been implemented on x86 platform. It needs mem-stores events and mem-loads/load-latency. For mem-stores events, it is MEM_INST_RETIRED_ALL_STORES whose raw number is r82d0, and mem-loads/load-latency is from PEBS if I follow its code. Now, for some arm64 cores, like HiSilicon's tsv110 and ARM's Neoverse N1, has supported the SPE(Statistical Profiling Extensions), so is it a possibility that perf-mem is supported on arm64? https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 For arm64 PMU, it has 'st_retired' event that the event number is 0x0007 which is equal to mem-stores on x86, if we want support perf-mem, it seems that 'st_retired' shall be replaced by 'mem-stores' in arch/arm64/kernel/perf_event.c file. Of course, the cpu core should support st_retired event. I'm not sure Will/Mark are happy on this.;-) For mem-loads/load-latency, we can derive them from SPE sampled data which supports by load_filter and min_latency in SPE driver. and we may do some work on tools/perf/builtin-mem.c. >From the above conditions, it seems that we may have the opportunity to support the perf-mem command on arm64. I'm not very sure about it, so I send this RFC and any comments are welcome. Thanks, Shaokun _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel