Re: [PATCH v5 04/12] coresight: etm4x: exclude ss_status from drvdata->config

[Jie Gan <jie.gan@oss.qualcomm.com>]

On 4/16/2026 2:54 PM, Yeoreum Yun wrote:
> Hi Jie,
> 

Hi Yeoreum,

>>
>>
>> On 4/16/2026 12:55 AM, Yeoreum Yun wrote:
>>> The purpose of TRCSSCSRn register is to show status of
>>> the corresponding Single-shot Comparator Control and input supports.
>>> That means writable field's purpose for reset or restore from idle status
>>> not for configuration.
>>>
>>> Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps
>>> and rename it to ss_smp.
>>>
>>> This includes remove TRCSSCRn from configurable item and
>>> remove saving in etm4_disable_hw().
>>>
>>> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
>>> ---
>>>    .../hwtracing/coresight/coresight-etm4x-cfg.c |  1 -
>>>    .../coresight/coresight-etm4x-core.c          | 19 ++++++-------------
>>>    .../coresight/coresight-etm4x-sysfs.c         |  7 ++-----
>>>    drivers/hwtracing/coresight/coresight-etm4x.h |  7 ++++++-
>>>    4 files changed, 14 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
>>> index c302072b293a..d14d7c8a23e5 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
>>> @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
>>>    		off_mask =  (offset & GENMASK(11, 5));
>>>    		do {
>>>    			CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
>>> -			CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
>>>    			CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
>>>    		} while (0);
>>>    	} else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>> index b2b092a76eb5..f55338a4989d 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>> @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
>>>    	const struct etmv4_caps *caps = &drvdata->caps;
>>>    	return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
>>> -	       (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
>>> +	       (caps->ss_cmp[n] & TRCSSCSRn_PC);
>>>    }
>>>    u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
>>> @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>>>    		etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
>>>    	for (i = 0; i < caps->nr_ss_cmp; i++) {
>>> -		/* always clear status bit on restart if using single-shot */
>>> -		if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
>>> -			config->ss_status[i] &= ~TRCSSCSRn_STATUS;
>>>    		etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
>>> -		etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
>>> +		/* always clear status and pending bits on restart if using single-shot */
>>> +		etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i));
>>>    		if (etm4x_sspcicrn_present(drvdata, i))
>>>    			etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
>>>    	}
>>> @@ -1055,12 +1053,6 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
>>>    	etm4_disable_trace_unit(drvdata);
>>> -	/* read the status of the single shot comparators */
>>> -	for (i = 0; i < caps->nr_ss_cmp; i++) {
>>> -		config->ss_status[i] =
>>> -			etm4x_relaxed_read32(csa, TRCSSCSRn(i));
>>> -	}
>>> -
>>>    	/* read back the current counter values */
>>>    	for (i = 0; i < caps->nr_cntr; i++) {
>>>    		config->cntr_val[i] =
>>> @@ -1503,8 +1495,9 @@ static void etm4_init_arch_data(void *info)
>>>    	 */
>>>    	caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
>>>    	for (i = 0; i < caps->nr_ss_cmp; i++) {
>>> -		drvdata->config.ss_status[i] =
>>> -			etm4x_relaxed_read32(csa, TRCSSCSRn(i));
>>> +		caps->ss_cmp[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
>>> +		caps->ss_cmp[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
>>> +				    TRCSSCSRn_DA | TRCSSCSRn_INST);
>>
>> Just re-go through this patch and had a question here:
>>
>> I’m not sure whether this new change should be documented in the ABI, given
>> that the TRCSSCSRn_STATUS bit is masked. In my opinion, this change breaks
>> the existing ABI description.
>>
>> Description from the ABI document:
>>
>> What:           /sys/bus/coresight/devices/etm<N>/sshot_status
>> Date:           December 2019
>> KernelVersion:  5.5
>> Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
>> Description:    (Read) Print the current value of the selected single
>>                  shot status register.
> 
> But, as I mentioned another thread:
>    - https://lore.kernel.org/all/ad5yV2FoNbGGLE6R@e129823.arm.com/
> 
> Till now, sysfs doesn't show the *current value* of the single shot
> state since the config->ss_status is updated enabled/disabled sysfs
> session. an I think once the session is disabled, other status bits
> (currently STATUS and PENDING bits) don't have any meaning.
> 
> I think it's enough to change the doc's Description for this.
> 
> Any thought?

Thanks for the info. I have missed this info, we are calling it 
'comparator' instead of 'status' by focusing on the capability bits.

Make sense to me.

Thanks,
Jie

> 
> --
> Sincerely,
> Yeoreum Yun