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From: Josua Mayer <josua@solid-run.com>
To: Shawn Guo <shawnguo@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Frank Li <frank.li@nxp.com>,
	Carlos Song <carlos.song@nxp.com>
Cc: Jon Nettleton <jon@solid-run.com>,
	Rabeeh Khoury <rabeeh@solid-run.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux@ew.tq-group.com" <linux@ew.tq-group.com>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH] arm64: dts: fsl-lx2160a: define pinctrl for iic2 sd-cd/-wp functions
Date: Sun, 13 Jul 2025 09:17:50 +0000	[thread overview]
Message-ID: <7579cb33-5006-4187-a868-c4ba9fb5cca8@solid-run.com> (raw)
In-Reply-To: <524f940e-9e31-411c-a419-cfb5a48d55ea@solid-run.com>

On 13/07/2025 11:24, Josua Mayer wrote:
> On 10/07/2025 18:09, Josua Mayer wrote:
>> LX2160 SoC uses a densely packed configuration area in memory for pin
>> muxing - configuring a variable number of IOs at a time.
>>
>> Since pinctrl nodes were added for the i2c signals of LX2160 SoC, boot
>> errors have been observed on SolidRun LX2162A Clearfog board when rootfs
>> is located on SD-Card (esdhc0):
>>
>> [    1.961035] mmc0: new ultra high speed SDR104 SDHC card at address 
>> aaaa
>> ...
>> [    5.220655] i2c i2c-1: using pinctrl states for GPIO recovery
>> [    5.226425] i2c i2c-1: using generic GPIOs for recovery
>> ...
>> [    5.440471] mmc0: card aaaa removed
>>
>> The card-detect and write-protect signals of esdhc0 are an alternate
>> function of IIC2 (in dts i2c1 - on lx2162 clearfog status disabled).
>>
>> By use of u-boot "md", and linux "devmem" command it was confirmed that
>> RCWSR12 (at 0x01e0012c) with IIC2_PMUX (at bits 0-2) changes from
>> 0x08000006 to 0x0000000 after starting Linux.
>
> compared values at 0x01e0012c (read-only) and 0x70010012c (dcfg).
>
>> This means that the card-detect pin function has changed to i2c function
>> - which will cause the controller to detect card removal.
>>
>> The respective i2c1-scl-pins node is only linked to i2c1 node that has
>> status disabled in device-tree for the solidrun boards.
>> How the memory is changed has not been investigated.
>
> RCWSR12 at 0x01e0012c is read-only and reflects the initial boot-time
> setting from RCW stage. The pinctrl-single driver uses dynamic
> configuration area at 0x70010012c to overide boot-time values.
>
> We found that the dynamic configuration address reads 0 before first
> write, hence when applying the first configuration the original non-zero
> value is lost.
>
> It might be worth reviewing and defining pinctrl for all alternate 
> functions
> of each i2c controller.
>
>> As a workaround add a new pinctrl definition for the
>> card-detect/write-protect function of IIC2 pins.
>> It seems unwise to link this directly from the SoC dtsi as boards may
>> rely on other functions such as flextimer.

After further thought I believe it better to revert the offending commit.
Any board that has status okay on either i2c[1-5] might have unintended
state on multiple pins since 8a1365c7bbc1.

On LX2162A Clearfog alone, the change broke both SD Card-Detect (IIC2_PMUX)
and SFP connector LEDs (SDHC1_DIR_PMUX).
However it is possible to also break IRQs, CAN, SPI and GPIOs - see 
below just
what the first 32-bit word at offset 12c controls:

08000006             = 0b0000100000000000 0000000000000110
IIC2_PMUX                  |||   |||   || |   |||   |||XXX : I2C/GPIO/CD-WP
IIC3_PMUX                  |||   |||   || |   |||   XXX    : 
I2C/GPIO/CAN/EVT
IIC4_PMUX                  |||   |||   || |   |||XXX       : 
I2C/GPIO/CAN/EVT
IIC5_PMUX                  |||   |||   || |   XXX          : 
I2C/GPIO/SDHC-CLK
IIC6_PMUX                  |||   |||   || |XXX             : 
I2C/GPIO/SDHC-CLK
XSPI1_A_DATA74_PMUX        |||   |||   XX X                : XSPI/GPIO
XSPI1_A_DATA30_PMUX        |||   |||XXX                    : XSPI/GPIO
XSPI1_A_BASE_PMUX          |||   XXX                       : XSPI/GPIO
SDHC1_BASE_PMUX            |||XXX                          : SDHC/GPIO/SPI
SDHC1_DIR_PMUX             XXX                             : SDHC/GPIO/SPI
RESERVED                 XX

 From QorIQ LX2160A Reference Manual Section 4.9.8.9
"Reset Control Word (RCW) Register Descriptions".

>>
>> Instead add the pinctrl to each board's esdhc0 node if it is known to
>> rely on native card-detect function. These boards have esdhc0 node
>> enabled and do not define broken-cd property:
>>
>> - fsl-lx2160a-bluebox3.dts
>> - fsl-lx2160a-clearfog-itx.dtsi
>> - fsl-lx2160a-qds.dts
>> - fsl-lx2160a-rdb.dts
>> - fsl-lx2160a-tqmlx2160a-mblx2160a.dts
>> - fsl-lx2162a-clearfog.dts
>> - fsl-lx2162a-qds.dts
>>
>> This was tested on the SolidRun LX2162 Clearfog with Linux v6.12.33.
>>
>> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
>> support bus recovery")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts | 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts | 
>> 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4
>> ++++
>> arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
>> arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 ++
>>    8 files changed, 18 insertions(+) 


      reply	other threads:[~2025-07-13  9:35 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-10 15:09 [PATCH] arm64: dts: fsl-lx2160a: define pinctrl for iic2 sd-cd/-wp functions Josua Mayer
2025-07-13  8:24 ` Josua Mayer
2025-07-13  9:17   ` Josua Mayer [this message]

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