From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27CABC433DB for ; Tue, 26 Jan 2021 12:50:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D7DDB2310E for ; Tue, 26 Jan 2021 12:50:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D7DDB2310E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xi9gEDyyYwoc0B1+3zG0tZRukHvD6UeDpjQCQKmKqpY=; b=NS59dzuC+oYoxumBDf0Ripdoh V9AxR5tzv83y44TESntceEPxXVmax3nSvispPVoFA07h3jIo38A/2yMIjQ33U4/SF7dYlbGURPsDU Umn2d1m1zD1NRX7LcvcXgfrKunp4Y3AF2KsnYjKjbJx9lmMetrUu0yHXT/pO09H6JF4BBRvAX57Kc W5NQnpYeb6ZmHjkT98qQMpZVX1jvO5W+r0PUn8P/yTHL6CdW1MqS58RqhcL5UuBLI4mxOMXqqmR+J tnbkY1lgzxg9hRvtB0SuBfVKvy1tbQ9xeEtU5OurAnZkWbngjd+/PZFwcYZj9niiyeRI4LUV/bGIJ GkvuNkmXQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l4Nlj-0001sn-Sz; Tue, 26 Jan 2021 12:48:27 +0000 Received: from frasgout.his.huawei.com ([185.176.79.56]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l4NkT-000159-0G for linux-arm-kernel@lists.infradead.org; Tue, 26 Jan 2021 12:47:10 +0000 Received: from fraeml711-chm.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4DQ5vK41VZz67gN9; Tue, 26 Jan 2021 20:41:17 +0800 (CST) Received: from lhreml724-chm.china.huawei.com (10.201.108.75) by fraeml711-chm.china.huawei.com (10.206.15.60) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 26 Jan 2021 13:47:06 +0100 Received: from [10.47.2.35] (10.47.2.35) by lhreml724-chm.china.huawei.com (10.201.108.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 26 Jan 2021 12:47:05 +0000 Subject: Re: [PATCH 7/8] drivers/perf: hisi: Add support for HiSilicon PA PMU driver To: Shaokun Zhang , References: <1609395576-32775-1-git-send-email-zhangshaokun@hisilicon.com> <1609395576-32775-8-git-send-email-zhangshaokun@hisilicon.com> From: John Garry Message-ID: <75d54612-c393-1355-8c21-36daa659b4fc@huawei.com> Date: Tue, 26 Jan 2021 12:45:44 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.1.2 MIME-Version: 1.0 In-Reply-To: <1609395576-32775-8-git-send-email-zhangshaokun@hisilicon.com> Content-Language: en-US X-Originating-IP: [10.47.2.35] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml724-chm.china.huawei.com (10.201.108.75) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210126_074709_308084_D567774A X-CRM114-Status: GOOD ( 31.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Qi Liu , Will Deacon , Jonathan Cameron Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 31/12/2020 06:19, Shaokun Zhang wrote: > On HiSilicon Hip09 platform, there is a PA (Protocol Adapter) module on > each chip SICL (Super I/O Cluster) which incorporates three Hydra interface > and facilitates the cache coherency between the dies on the chip. While PA > uncore PMU model is the same as other Hip09 PMU modules and many PMU events > are supported. Let's support the PMU driver using the HiSilicon uncore PMU > framework. > > Cc: Mark Rutland > Cc: Will Deacon > Cc: John Garry > Cc: Jonathan Cameron > Co-developed-by: Qi Liu > Signed-off-by: Qi Liu > Signed-off-by: Shaokun Zhang nit: please stop using inline when not needed Apart from minor comments, below: Reviewed-by: John Garry note: we do internal review, but tags not given - maybe we should in future... > --- > drivers/perf/hisilicon/Makefile | 3 +- > drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 498 ++++++++++++++++++++++++++++ > include/linux/cpuhotplug.h | 1 + > 3 files changed, 501 insertions(+), 1 deletion(-) > create mode 100644 drivers/perf/hisilicon/hisi_uncore_pa_pmu.c > > diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile > index 6600a9d45dd8..7643c9f93e36 100644 > --- a/drivers/perf/hisilicon/Makefile > +++ b/drivers/perf/hisilicon/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o \ > - hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o hisi_uncore_sllc_pmu.o > + hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o hisi_uncore_sllc_pmu.o \ > + hisi_uncore_pa_pmu.o > diff --git a/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c > new file mode 100644 > index 000000000000..eec12f5daf71 > --- /dev/null > +++ b/drivers/perf/hisilicon/hisi_uncore_pa_pmu.c > @@ -0,0 +1,498 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * HiSilicon PA uncore Hardware event counters support > + * > + * Copyright (C) 2020 HiSilicon Limited > + * Author: Shaokun Zhang > + * > + * This code is based on the uncore PMUs like arm-cci and arm-ccn. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "hisi_uncore_pmu.h" > + > +/* PA register definition */ > +#define PA_PERF_CTRL 0x1C00 nit: generally lower case used for hex, but not so important > +#define PA_EVENT_CTRL 0x1C04 > +#define PA_TT_CTRL 0x1C08 > +#define PA_TGTID_CTRL 0x1C14 > +#define PA_SRCID_CTRL 0x1C18 > +#define PA_INT_MASK 0x1C70 > +#define PA_INT_STATUS 0x1C78 > +#define PA_INT_CLEAR 0x1C7C > +#define PA_EVENT_TYPE0 0x1C80 > +#define PA_PMU_VERSION 0x1CF0 > +#define PA_EVENT_CNT0_L 0x1D00 > + ... > + > +static int hisi_pa_pmu_init_data(struct platform_device *pdev, > + struct hisi_pmu *pa_pmu) > +{ > + /* > + * Use the SCCL_ID and the index ID to identify the PA PMU, > + * while SCCL_ID is the nearst SCCL_ID from this SICL. > + */ > + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id", > + &pa_pmu->sccl_id)) { hmmm... I do wonder if we should make it clearer in the driver that this is the SICL. I know I mentioned this before--sorry > + dev_err(&pdev->dev, "Cannot read sccl-id!\n"); > + return -EINVAL; > + } > + > + if (device_property_read_u32(&pdev->dev, "hisilicon,idx-id", > + &pa_pmu->index_id)) { > + dev_err(&pdev->dev, "Cannot read idx-id!\n"); > + return -EINVAL; > + } > + > + pa_pmu->ccl_id = -1; > + > + pa_pmu->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(pa_pmu->base)) { > + dev_err(&pdev->dev, "ioremap failed for pa_pmu resource.\n"); > + return PTR_ERR(pa_pmu->base); > + } > + > + pa_pmu->identifier = readl(pa_pmu->base + PA_PMU_VERSION); > + > + return 0; > +} > + ... > +static int hisi_pa_pmu_probe(struct platform_device *pdev) > +{ > + struct hisi_pmu *pa_pmu; > + char *name; > + int ret; > + > + pa_pmu = devm_kzalloc(&pdev->dev, sizeof(*pa_pmu), GFP_KERNEL); > + if (!pa_pmu) > + return -ENOMEM; > + > + ret = hisi_pa_pmu_dev_probe(pdev, pa_pmu); > + if (ret) > + return ret; > + /* > + * PA is attached in SICL and the CPU core is chosen to manage this > + * PMU which is the nearest SCCL, do we really need to do this? Can any CPU in that chip do it? > while its SCCL_ID is greater than > + * one with the SICL_ID. > + */ > + name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sicl%u_pa%u", > + pa_pmu->sccl_id - 1, pa_pmu->index_id); > + if (!name) { > + dev_err(&pdev->dev, "failed to allocate name for PMU\n"); > + return -ENOMEM; > + } > + > + ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, > + &pa_pmu->node); > + if (ret) { > + dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); > + return ret; > + } > + > + pa_pmu->pmu = (struct pmu) { > + .module = THIS_MODULE, > + .task_ctx_nr = perf_invalid_context, > + .event_init = hisi_uncore_pmu_event_init, > + .pmu_enable = hisi_uncore_pmu_enable, > + .pmu_disable = hisi_uncore_pmu_disable, > + .add = hisi_uncore_pmu_add, > + .del = hisi_uncore_pmu_del, > + .start = hisi_uncore_pmu_start, > + .stop = hisi_uncore_pmu_stop, > + .read = hisi_uncore_pmu_read, > + .attr_groups = pa_pmu->pmu_events.attr_groups, > + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, > + }; > + > + ret = perf_pmu_register(&pa_pmu->pmu, name, -1); > + if (ret) { > + dev_err(pa_pmu->dev, "PMU register failed, ret = %d\n", ret); > + cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, > + &pa_pmu->node); > + irq_set_affinity_hint(pa_pmu->irq, NULL); > + } > + > + platform_set_drvdata(pdev, pa_pmu); as before > + return ret; > +} > + > +static int hisi_pa_pmu_remove(struct platform_device *pdev) > +{ > + struct hisi_pmu *pa_pmu = platform_get_drvdata(pdev); > + > + perf_pmu_unregister(&pa_pmu->pmu); > + cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, > + &pa_pmu->node); > + irq_set_affinity_hint(pa_pmu->irq, NULL); > + > + return 0; > +} > + > +static struct platform_driver hisi_pa_pmu_driver = { > + .driver = { > + .name = "hisi_pa_pmu", > + .acpi_match_table = hisi_pa_pmu_acpi_match, some small comments on earlier patch reviews apply here > + }, > + .probe = hisi_pa_pmu_probe, > + .remove = hisi_pa_pmu_remove, > +}; > + > +static int __init hisi_pa_pmu_module_init(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, > + "AP_PERF_ARM_HISI_PA_ONLINE", > + hisi_uncore_pmu_online_cpu, > + hisi_uncore_pmu_offline_cpu); > + if (ret) { > + pr_err("PA PMU: cpuhp state setup failed, ret = %d\n", ret); > + return ret; > + } > + > + ret = platform_driver_register(&hisi_pa_pmu_driver); > + if (ret) > + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE); > + > + return ret; > +} > +module_init(hisi_pa_pmu_module_init); > + > +static void __exit hisi_pa_pmu_module_exit(void) > +{ > + platform_driver_unregister(&hisi_pa_pmu_driver); > + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_PA_ONLINE); > +} > +module_exit(hisi_pa_pmu_module_exit); > + > +MODULE_DESCRIPTION("HiSilicon PA uncore PMU driver"); nit maybe have "PA (Protocol Adapter)" > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Shaokun Zhang "); > diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h > index b5e04f9b68f1..37f591ed80d0 100644 > --- a/include/linux/cpuhotplug.h > +++ b/include/linux/cpuhotplug.h > @@ -174,6 +174,7 @@ enum cpuhp_state { > CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE, > CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE, > CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, > + CPUHP_AP_PERF_ARM_HISI_PA_ONLINE, > CPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE, > CPUHP_AP_PERF_ARM_L2X0_ONLINE, > CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE, > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel