[PATCH v2] arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model

[PATCH v2] arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model

[Leo Yan]

The FVP Rev C model includes CoreSight ETE and TRBE support.  These
features can be enabled by specifying parameters when launching the
model:

  -C cluster0.has_ete: 1
  -C cluster1.has_ete: 1
  -C cluster0.has_trbe: 1
  -C cluster1.has_trbe: 1

This change adds device tree bindings for the ETE and TRBE nodes.  They
are disabled by default to prevent kernel warnings from failed driver
probes, as the model does not enable the features unless explicitly
specified.

Signed-off-by: Leo Yan <leo.yan@arm.com>
---

Changes from v1:
- Removed the property "arm,coresight-loses-context-with-cpu" from ETE
  nodes.
- Updated ETE node name for compliance with the DT spec.

 arch/arm64/boot/dts/arm/fvp-base-revc.dts | 54 +++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index 9e10d7a6b5a2..a71098f74609 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -227,6 +227,60 @@ spe-pmu {
 		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	ete-0 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu0>;
+		status = "disabled";
+	};
+
+	ete-1 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu1>;
+		status = "disabled";
+	};
+
+	ete-2 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu2>;
+		status = "disabled";
+	};
+
+	ete-3 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu3>;
+		status = "disabled";
+	};
+
+	ete-4 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu4>;
+		status = "disabled";
+	};
+
+	ete-5 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu5>;
+		status = "disabled";
+	};
+
+	ete-6 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu6>;
+		status = "disabled";
+	};
+
+	ete-7 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu7>;
+		status = "disabled";
+	};
+
+	trbe {
+		compatible = "arm,trace-buffer-extension";
+		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_LOW>;
+		status = "disabled";
+	};
+
 	pci: pci@40000000 {
 		#address-cells = <0x3>;
 		#size-cells = <0x2>;
-- 
2.34.1

Re: [PATCH v2] arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model

[Suzuki K Poulose]

On 12/05/2025 16:11, Leo Yan wrote:
> The FVP Rev C model includes CoreSight ETE and TRBE support.  These
> features can be enabled by specifying parameters when launching the
> model:
> 
>    -C cluster0.has_ete: 1
>    -C cluster1.has_ete: 1
>    -C cluster0.has_trbe: 1
>    -C cluster1.has_trbe: 1
> 
> This change adds device tree bindings for the ETE and TRBE nodes.  They
> are disabled by default to prevent kernel warnings from failed driver
> probes, as the model does not enable the features unless explicitly
> specified.
> 
> Signed-off-by: Leo Yan <leo.yan@arm.com>

Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Re: [PATCH v2] arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model

[Sudeep Holla]

On Mon, 12 May 2025 16:11:49 +0100, Leo Yan wrote:
> The FVP Rev C model includes CoreSight ETE and TRBE support.  These
> features can be enabled by specifying parameters when launching the
> model:
> 
>   -C cluster0.has_ete: 1
>   -C cluster1.has_ete: 1
>   -C cluster0.has_trbe: 1
>   -C cluster1.has_trbe: 1
> 
> [...]

Applied to sudeep.holla/linux (for-next/juno/updates), thanks!

[1/1] arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model
      https://git.kernel.org/sudeep.holla/c/6332351622db
--
Regards,
Sudeep