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bh=KoAAYwwSkct1dybDxwgNyk2Rm0SbhKgSXVNFxBcKatM=; b=I2lRGJfqsloGT2SHdY2M8bMV7/q4Pr59f484nUVBeklXjYgpLKNPtR3atxbCXVW/1M6/d1 //HA5XXVaNuD2b6Enca6KnfDPJxqBmUJVqa4NOLPhPFCNkGxeddmE1IsXzMp3cd3fDxZa9 4Wf2yOBB5cqHG01UPn+ngvQ1D/DdhFnwzrgHDLLlrUCNHJ2+CF+eucPncmiU2dFK1Xd5zj 1bqiFG5NNt+0uzUK50KJiBMdN5ZwIGz4mp4wdPyVgLVCJat/0ddlHGrXzVsca75CD+dH9o jexbeP8s6jXf3KHK5o6c3HwCeYSfw964x6dFHgdaUjHVmUad+JjZ9p3epDuIHA== Message-ID: <78249155-c90a-4c33-8caa-d79d83171551@mailbox.org> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1760538811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KoAAYwwSkct1dybDxwgNyk2Rm0SbhKgSXVNFxBcKatM=; b=I/FcsianBv0Nxyf1djQKC/ndDM6D04GOPsXWCbJsRR8sd9AASeOicPZ6iFlUcdZQ5lOzOD Ja5w1TTbFN+8hn/CISsFQbHxB7aDwsVIp1/ltJEvascotKjnWLppiDSkL0ALI5UeGqpeDJ VjQca0ofS305cN2uQPwlJRtSOCiviTS/QR5G0ui17dOZgAUEzdgfYD5NVntVYPWcw21Pz1 6LzaB30f84Cgzsz1dU5n4QmbfXG9yQpY+e8Jtp/H2lEvSCoD+car8jueuek8SJfo4QkP1S Yqi8gLvqHlDHg9MF2IAX9amcKfIRtY0TXLBtsfkM2aIM04bBzGFYS5+lLWccYA== Date: Wed, 15 Oct 2025 16:32:24 +0200 MIME-Version: 1.0 Subject: Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node To: Matt Coster , Marek Vasut Cc: Adam Ford , Conor Dooley , David Airlie , Frank Binns , Alessio Belle , Alexandru Dadu , Geert Uytterhoeven , Krzysztof Kozlowski , Kuninori Morimoto , Maarten Lankhorst , Magnus Damm , Maxime Ripard , Rob Herring , Simona Vetter , Thomas Zimmermann , "devicetree@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linux-arm-kernel@lists.infradead.org" , "linux-renesas-soc@vger.kernel.org" References: <20251013190210.142436-1-marek.vasut+renesas@mailbox.org> <20251013190210.142436-2-marek.vasut+renesas@mailbox.org> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-META: c1dy1jmb5s88yb7q9s43rwqiniopzzh7 X-MBO-RS-ID: fb5ef80d27592a90e0c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251015_073336_707732_85479993 X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/15/25 12:55 PM, Matt Coster wrote: Hello Matt, >>> I see this pattern used throughout >>> the Renesas dts, but I'm just thinking how this will interact with the >>> powervr driver. The reset line is optional since some hardware >>> integrations manage it for us during the power-up/down sequences, which >>> appears to be the case here with the MSTP control (from my brief dig >>> through the Renesas TRM). >> >> As far as I can tell, the pvr_power.c toggles the IP reset after the >> IP clock were already enabled, so the IP should be correctly reset. >> What kind of problem do you expect ? > > I think I'm just being paranoid about the weirdness (to me at least) of > having one device be treated as both clock and reset line. Assuming this > is tested as working, I'm okay with it, especially as it seems to be the > norm for Renesas. The combined clock/reset IP is not limited to renesas SoCs, there are other SoCs which do the same thing (Allwinner "ccu", Marvell PXA "soc_clocks" , nVidia Tegra "car", Qualcomm "gcc", Rockchip "cru", to name a few). Usually the registers which control clock and resets are shared in the same IP, but they control different (possibly related) signals in the SoC. >>> Related, see my comments on the bindings patch (P1/3) about how clocks >>> are wired up in this SoC. >> I tried to reply to that one, hopefully it makes some sense. > > Looks like we've figured it out there, thanks for your comments! Likewise, thank you for sharing the clocking details. -- Best regards, Marek Vasut