[PATCH v2 0/4] ARM: rockchip: add dma support

[PATCH v2 0/4] ARM: rockchip: add dma support

[Heiko Stübner]

All Rockchip SoCs currently supported use pl330 dma controllers.
The first patch introduces the concept of critical clocks, stolen from
sunxi, as some core clocks shouldn't be disabled under normal circumstances.
The patch is necessary, as the amba bus uses strict clock gating, which
without this patch results in the core aclk getting disabled halting the
system, before other components are able to probe and maybe claim their
clocks.

As the patches have no compile-time dependency on each other, the patchset
could be split with the first patch going through the clock tree and the
other three going through arm-soc.

changes since v1:
- address comment Sergei Shtylyov and rename nodes to dma-controller
- address comments from Doug Anderson:
  - order by address
  - rename the controller phandles to reflect the naming in the TRMs
    On the rk3066/rk3188 there is one diversion in this regard.
    The clocks really use indices 1 and 2 while the controllers references
    use 0 and 1 (dmac0 and dmac1), so to prevent to much confusion I used
    the clock indices for the handles instead of having dmac0 use ACLK_DMAC1
    etc.
- address comment from Andreas F?rber adding suffixes of "_s" for the
  secure and "_ns" for the non-secure variants of the first controller
  As (nearly) all boards seem to use the secure controller, this becomes
  the default

Heiko Stuebner (4):
  clk: rockchip: protect critical clocks from getting disabled
  ARM: rockchip: enable the AMBA bus
  ARM: dts: rockchip: add rk3288 dma controllers
  ARM: dts: rockchip: add rk3188 dma controllers

 arch/arm/boot/dts/rk3288.dtsi     | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi     | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/Kconfig    |  1 +
 drivers/clk/rockchip/clk-rk3188.c |  7 +++++++
 drivers/clk/rockchip/clk-rk3288.c |  7 +++++++
 drivers/clk/rockchip/clk.c        | 13 +++++++++++++
 drivers/clk/rockchip/clk.h        |  1 +
 7 files changed, 105 insertions(+)

-- 
1.9.0

[PATCH v2 1/4] clk: rockchip: protect critical clocks from getting disabled

[Heiko Stübner]

The clock-tree contains clocks that should never get disabled automatically.
One example are the base ACLKs, the base supplies for all peripherals.

Therefore add a structure similar to the sunxi clock-tree to protect these
special clocks from being disabled.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
---
no change since v1

 drivers/clk/rockchip/clk-rk3188.c |  7 +++++++
 drivers/clk/rockchip/clk-rk3288.c |  7 +++++++
 drivers/clk/rockchip/clk.c        | 13 +++++++++++++
 drivers/clk/rockchip/clk.h        |  1 +
 4 files changed, 28 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index a83a6d8..732118e 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -599,6 +599,11 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 	GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
 };
 
+static const char *rk3188_critical_clocks[] __initconst = {
+	"aclk_cpu",
+	"aclk_peri",
+};
+
 static void __init rk3188_common_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
@@ -628,6 +633,8 @@ static void __init rk3188_common_clk_init(struct device_node *np)
 				   RK3188_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(common_clk_branches,
 				  ARRAY_SIZE(common_clk_branches));
+	rockchip_clk_protect_critical(rk3188_critical_clocks,
+				      ARRAY_SIZE(rk3188_critical_clocks));
 
 	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 0d8c6c5..038b1aa 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -680,6 +680,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
 };
 
+static const char *rk3288_critical_clocks[] __initconst = {
+	"aclk_cpu",
+	"aclk_peri",
+};
+
 static void __init rk3288_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
@@ -710,6 +715,8 @@ static void __init rk3288_clk_init(struct device_node *np)
 				   RK3288_GRF_SOC_STATUS);
 	rockchip_clk_register_branches(rk3288_clk_branches,
 				  ARRAY_SIZE(rk3288_clk_branches));
+	rockchip_clk_protect_critical(rk3288_critical_clocks,
+				      ARRAY_SIZE(rk3288_critical_clocks));
 
 	rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 278cf9d..9189f1b 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -242,3 +242,16 @@ void __init rockchip_clk_register_branches(
 		rockchip_clk_add_lookup(clk, list->id);
 	}
 }
+
+void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks)
+{
+	int i;
+
+	/* Protect the clocks that needs to stay on */
+	for (i = 0; i < nclocks; i++) {
+		struct clk *clk = __clk_lookup(clocks[i]);
+
+		if (clk)
+			clk_prepare_enable(clk);
+	}
+}
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 887cbde..2b0bca1 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -329,6 +329,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
 				    unsigned int nr_clk);
 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
 				unsigned int nr_pll, int grf_lock_offset);
+void rockchip_clk_protect_critical(const char *clocks[], int nclocks);
 
 #define ROCKCHIP_SOFTRST_HIWORD_MASK	BIT(0)
 
-- 
1.9.0

[PATCH v2 2/4] ARM: rockchip: enable the AMBA bus

[Heiko Stübner]

This is needed to access the pl330 dma controllers on Rockchip SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
---
 arch/arm/mach-rockchip/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d168669..ac5803c 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -4,6 +4,7 @@ config ARCH_ROCKCHIP
 	select PINCTRL_ROCKCHIP
 	select ARCH_HAS_RESET_CONTROLLER
 	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
 	select ARM_GIC
 	select CACHE_L2X0
 	select HAVE_ARM_ARCH_TIMER
-- 
1.9.0

[PATCH v2 3/4] ARM: dts: rockchip: add rk3288 dma controllers

[Heiko Stübner]

Add both the bus and peripheral pl330 dma controllers present in rk3288 socs.
The first dma controller can change between secure and non-secure mode. Both
instances are added but the non-secure variant is left disabled by default,
as on the majority of boards the bootloader leaves it in secure mode.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3288.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a..add0e11 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -62,6 +62,44 @@
 		};
 	};
 
+	amba {
+		compatible = "arm,amba-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		dmac_peri: dma-controller at ff250000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xff250000 0x4000>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMAC2>;
+			clock-names = "apb_pclk";
+		};
+
+		dmac_bus_ns: dma-controller at ff600000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xff600000 0x4000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMAC1>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		dmac_bus_s: dma-controller at ffb20000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xffb20000 0x4000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMAC1>;
+			clock-names = "apb_pclk";
+		};
+	};
+
 	xin24m: oscillator {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
-- 
1.9.0

[PATCH v2 4/4] ARM: dts: rockchip: add rk3066 and rk3188 dma controllers

[Heiko Stübner]

Add both the cpu and peripheral pl330 dma controllers present in rk3188 socs.
The first dma controller can change between secure and non-secure mode. Both
instances are added but the non-secure variant is left disabled by default,
as on the majority of boards the bootloader leaves it in secure mode.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3xxx.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 8caf85d..b5bd3a6 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -28,6 +28,44 @@
 		i2c4 = &i2c4;
 	};
 
+	amba {
+		compatible = "arm,amba-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		dmac1_s: dma-controller at 20018000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x20018000 0x4000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMA1>;
+			clock-names = "apb_pclk";
+		};
+
+		dmac1_ns: dma-controller at 2001c000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x2001c000 0x4000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMA1>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		dmac2: dma-controller at 20078000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x20078000 0x4000>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMA2>;
+			clock-names = "apb_pclk";
+		};
+	};
+
 	xin24m: oscillator {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
-- 
1.9.0

[PATCH v2 1/4] clk: rockchip: protect critical clocks from getting disabled

[Heiko Stübner]

Hi Mike,

Am Donnerstag, 14. August 2014, 23:00:26 schrieb Heiko St?bner:
> The clock-tree contains clocks that should never get disabled automatically.
> One example are the base ACLKs, the base supplies for all peripherals.
> 
> Therefore add a structure similar to the sunxi clock-tree to protect these
> special clocks from being disabled.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Kever Yang <kever.yang@rock-chips.com>
> ---

from the discussions in v1 I remember there were no showstoppers for this 
change, so could take a look into applying this one patch, so we can 
sucessfully enable the dma controllers :-)


Thanks
Heiko


> no change since v1
> 
>  drivers/clk/rockchip/clk-rk3188.c |  7 +++++++
>  drivers/clk/rockchip/clk-rk3288.c |  7 +++++++
>  drivers/clk/rockchip/clk.c        | 13 +++++++++++++
>  drivers/clk/rockchip/clk.h        |  1 +
>  4 files changed, 28 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3188.c
> b/drivers/clk/rockchip/clk-rk3188.c index a83a6d8..732118e 100644
> --- a/drivers/clk/rockchip/clk-rk3188.c
> +++ b/drivers/clk/rockchip/clk-rk3188.c
> @@ -599,6 +599,11 @@ static struct rockchip_clk_branch rk3188_clk_branches[]
> __initdata = { GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0,
> RK2928_CLKGATE_CON(8), 13, GFLAGS), };
> 
> +static const char *rk3188_critical_clocks[] __initconst = {
> +	"aclk_cpu",
> +	"aclk_peri",
> +};
> +
>  static void __init rk3188_common_clk_init(struct device_node *np)
>  {
>  	void __iomem *reg_base;
> @@ -628,6 +633,8 @@ static void __init rk3188_common_clk_init(struct
> device_node *np) RK3188_GRF_SOC_STATUS);
>  	rockchip_clk_register_branches(common_clk_branches,
>  				  ARRAY_SIZE(common_clk_branches));
> +	rockchip_clk_protect_critical(rk3188_critical_clocks,
> +				      ARRAY_SIZE(rk3188_critical_clocks));
> 
>  	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
>  				  ROCKCHIP_SOFTRST_HIWORD_MASK);
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index 0d8c6c5..038b1aa 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -680,6 +680,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = { GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16),
> 3, GFLAGS), };
> 
> +static const char *rk3288_critical_clocks[] __initconst = {
> +	"aclk_cpu",
> +	"aclk_peri",
> +};
> +
>  static void __init rk3288_clk_init(struct device_node *np)
>  {
>  	void __iomem *reg_base;
> @@ -710,6 +715,8 @@ static void __init rk3288_clk_init(struct device_node
> *np) RK3288_GRF_SOC_STATUS);
>  	rockchip_clk_register_branches(rk3288_clk_branches,
>  				  ARRAY_SIZE(rk3288_clk_branches));
> +	rockchip_clk_protect_critical(rk3288_critical_clocks,
> +				      ARRAY_SIZE(rk3288_critical_clocks));
> 
>  	rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
>  				  ROCKCHIP_SOFTRST_HIWORD_MASK);
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index 278cf9d..9189f1b 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -242,3 +242,16 @@ void __init rockchip_clk_register_branches(
>  		rockchip_clk_add_lookup(clk, list->id);
>  	}
>  }
> +
> +void __init rockchip_clk_protect_critical(const char *clocks[], int
> nclocks) +{
> +	int i;
> +
> +	/* Protect the clocks that needs to stay on */
> +	for (i = 0; i < nclocks; i++) {
> +		struct clk *clk = __clk_lookup(clocks[i]);
> +
> +		if (clk)
> +			clk_prepare_enable(clk);
> +	}
> +}
> diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
> index 887cbde..2b0bca1 100644
> --- a/drivers/clk/rockchip/clk.h
> +++ b/drivers/clk/rockchip/clk.h
> @@ -329,6 +329,7 @@ void rockchip_clk_register_branches(struct
> rockchip_clk_branch *clk_list, unsigned int nr_clk);
>  void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
>  				unsigned int nr_pll, int grf_lock_offset);
> +void rockchip_clk_protect_critical(const char *clocks[], int nclocks);
> 
>  #define ROCKCHIP_SOFTRST_HIWORD_MASK	BIT(0)

[PATCH v2 0/4] ARM: rockchip: add dma support

[Heiko Stübner]

Am Donnerstag, 14. August 2014, 22:59:48 schrieb Heiko St?bner:
> All Rockchip SoCs currently supported use pl330 dma controllers.
> The first patch introduces the concept of critical clocks, stolen from
> sunxi, as some core clocks shouldn't be disabled under normal circumstances.
> The patch is necessary, as the amba bus uses strict clock gating, which
> without this patch results in the core aclk getting disabled halting the
> system, before other components are able to probe and maybe claim their
> clocks.
> 
> As the patches have no compile-time dependency on each other, the patchset
> could be split with the first patch going through the clock tree and the
> other three going through arm-soc.

I've add the patches 2-4 to a v3.18-next/dma branch.


> 
> changes since v1:
> - address comment Sergei Shtylyov and rename nodes to dma-controller
> - address comments from Doug Anderson:
>   - order by address
>   - rename the controller phandles to reflect the naming in the TRMs
>     On the rk3066/rk3188 there is one diversion in this regard.
>     The clocks really use indices 1 and 2 while the controllers references
>     use 0 and 1 (dmac0 and dmac1), so to prevent to much confusion I used
>     the clock indices for the handles instead of having dmac0 use ACLK_DMAC1
> etc.
> - address comment from Andreas F?rber adding suffixes of "_s" for the
>   secure and "_ns" for the non-secure variants of the first controller
>   As (nearly) all boards seem to use the secure controller, this becomes
>   the default
> 
> Heiko Stuebner (4):
>   clk: rockchip: protect critical clocks from getting disabled
>   ARM: rockchip: enable the AMBA bus
>   ARM: dts: rockchip: add rk3288 dma controllers
>   ARM: dts: rockchip: add rk3188 dma controllers
> 
>  arch/arm/boot/dts/rk3288.dtsi     | 38
> ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi     |
> 38 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig   
> |  1 +
>  drivers/clk/rockchip/clk-rk3188.c |  7 +++++++
>  drivers/clk/rockchip/clk-rk3288.c |  7 +++++++
>  drivers/clk/rockchip/clk.c        | 13 +++++++++++++
>  drivers/clk/rockchip/clk.h        |  1 +
>  7 files changed, 105 insertions(+)