From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow
Date: Wed, 08 Jul 2015 10:58:55 +0200 [thread overview]
Message-ID: <79801022.IfOq8aeLEc@diego> (raw)
In-Reply-To: <1436344666-25645-2-git-send-email-jamesjj.liao@mediatek.com>
Am Mittwoch, 8. Juli 2015, 16:37:45 schrieb James Liao:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
>
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
>
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
next prev parent reply other threads:[~2015-07-08 8:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-08 8:37 [PATCH 0/2] Add MT8173 MMPLL change rate support James Liao
2015-07-08 8:37 ` [PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow James Liao
2015-07-08 8:58 ` Heiko Stübner [this message]
2015-07-08 8:37 ` [PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support James Liao
2015-07-09 0:46 ` Stephen Boyd
2015-07-10 5:46 ` James Liao
2015-07-08 8:49 ` [PATCH 0/2] " James Liao
2015-07-09 0:44 ` Stephen Boyd
2015-07-10 5:44 ` James Liao
2015-07-14 22:13 ` Stephen Boyd
2015-07-15 9:51 ` James Liao
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