From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D56BCCFA1A for ; Wed, 12 Nov 2025 01:04:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:To:Subject:Cc:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=X0Bnr2iJChPdZ80UCVLiI+51ilZQPsF7USzqD4IyGeA=; b=DBKgyzsDRpTRZBHC4L4+5BzLxN 7OzkR5ij31x9JJ0TomDp/SfYz7+y9acDAAkJ+HduyXj2LN3SgH1V+ZPS22NfubhQy1jqR783QyzCI /SywE3Zzp/hXTurLVXptMMqf6F27f4A+oD005NW0ilwDBRO10R+vNcnm5EJxf81wIxVJ358L7HGCB 8cfHNAeTtDiTGJgPhZkNtfv5pqtNUy+/QAgugHdqVEU5EZSUF5TkxJeX4Vu3UP5rwrSA6yR/HV+wQ J36ngD/15Onw3anG5UIUU7507EzszcEVtKuWBXXcwOlnj2Lya8Y96HzxgGX68Mqb4P0u1OkS75FPI xuBawNKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vIzH3-00000007wZW-2PBj; Wed, 12 Nov 2025 01:03:49 +0000 Received: from mail-m49238.qiye.163.com ([45.254.49.238]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vIzH0-00000007wYs-2F1G; Wed, 12 Nov 2025 01:03:48 +0000 Received: from [192.168.61.151] (unknown [110.83.51.2]) by smtp.qiye.163.com (Hmail) with ESMTP id 293fd660a; Wed, 12 Nov 2025 09:03:42 +0800 (GMT+08:00) Message-ID: <79a8c3cc-2b60-4bce-b1ba-7ab5f033f924@rock-chips.com> Date: Wed, 12 Nov 2025 09:03:38 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Heiko Stuebner , Kever Yang , Simon Xue , Damien Le Moal , Dragan Simic , FUKAUMI Naoki , Diederik de Haas , Richard Zhu , Frank Li , Lucas Stach , Shawn Guo , Sascha Hauer , Fabio Estevam , Conor Dooley , Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter , Hans Zhang , linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@pengutronix.de, Bjorn Helgaas , Niklas Cassel Subject: Re: [PATCH 1/4] PCI: dwc: Advertise L1 PM Substates only if driver requests it To: Bjorn Helgaas References: <20251111221621.2208606-1-helgaas@kernel.org> <20251111221621.2208606-2-helgaas@kernel.org> From: Shawn Lin In-Reply-To: <20251111221621.2208606-2-helgaas@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9a759702a009cckunm68f60faf90264 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaTUNNVkxJSRoZGR5KTRoaHlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSktVQ0hVTkpVSVlXWRYaDxIVHRRZQVlPS0hVSktISkpCTVVKS0tVSk JZBg++ DKIM-Signature: a=rsa-sha256; b=DNa5Gs7krwEhPUprrj/3XgxdSRjNLBnw+qN8B4C1vhJlTX/vfffYkqXOnhtb/6isIcgYPxadD7Z2X5DoSALMwp3BimgGwfur5wMUdCPUpgAhoDNn1bx0HLtK5uyLXSstW6gi7Ky7ThJ0IqZ6g1wO8KJqM501+F+nkx1fxrx3axo=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=X0Bnr2iJChPdZ80UCVLiI+51ilZQPsF7USzqD4IyGeA=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251111_170347_041906_4D902115 X-CRM114-Status: GOOD ( 25.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 在 2025/11/12 星期三 6:16, Bjorn Helgaas 写道: > From: Bjorn Helgaas > > L1 PM Substates require the CLKREF# signal and may also require > device-specific support. If CLKREF# is not supported or driver support is > lacking, enabling L1.1 or L1.2 may cause errors when accessing devices, > e.g., > > nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0x10 > > If the kernel is built with CONFIG_PCIEASPM_POWER_SUPERSAVE=y or users > enable L1.x via sysfs, users may trip over these errors even if L1 > Substates haven't been enabled by firmware or the driver. > > To prevent such errors, disable advertising the L1 PM Substates unless the > driver sets "dw_pcie.l1ss_support" to indicate that it knows CLKREF# is > present and any device-specific configuration has been done. > > Set "dw_pcie.l1ss_support" in tegra194 (if DT includes the > "supports-clkreq' property) and qcom (for 2.7.0 controllers) so they can > continue to use L1 Substates. > > Based on Niklas's patch: > https://patch.msgid.link/20251017163252.598812-2-cassel@kernel.org Except the issue Fank pointed out, the commit msg says CLKREF# 3 times which seems not a term from spec. Should it be CLKREQ# ? Otherwise, Reviewed-by: Shawn Lin > > Signed-off-by: Bjorn Helgaas > --- > .../pci/controller/dwc/pcie-designware-ep.c | 2 ++ > .../pci/controller/dwc/pcie-designware-host.c | 2 ++ > drivers/pci/controller/dwc/pcie-designware.c | 24 +++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ > drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ > 6 files changed, 35 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 7f2112c2fb21..c94cff6eeb01 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -966,6 +966,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) > if (ep->ops->init) > ep->ops->init(ep); > > + dw_pcie_config_l1ss(pci); > + > ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); > > /* > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 20c9333bcb1c..f1d5b45a3214 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -1060,6 +1060,8 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > PCI_COMMAND_MASTER | PCI_COMMAND_SERR; > dw_pcie_writel_dbi(pci, PCI_COMMAND, val); > > + dw_pcie_config_l1ss(pci); > + > dw_pcie_config_presets(pp); > /* > * If the platform provides its own child bus config accesses, it means > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index c644216995f6..ede686623fad 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -1081,6 +1081,30 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) > dw_edma_remove(&pci->edma); > } > > +void dw_pcie_config_l1ss(struct dw_pcie *pci) > +{ > + u16 l1ss; > + u32 l1ss_cap; > + > + if (!pci->l1ss_support) > + return; > + > + l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); > + if (!l1ss) > + return; > + > + /* > + * Unless the driver claims "l1ss_support", don't advertise L1 PM > + * Substates because they require CLKREF# and possibly other > + * device-specific configuration. > + */ > + l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); > + l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | > + PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | > + PCI_L1SS_CAP_L1_PM_SS); > + dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); > +} > + > void dw_pcie_setup(struct dw_pcie *pci) > { > u32 val; > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index e995f692a1ec..8d14b1fe2280 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -516,6 +516,7 @@ struct dw_pcie { > int max_link_speed; > u8 n_fts[2]; > struct dw_edma_chip edma; > + bool l1ss_support; /* L1 PM Substates support */ > struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS]; > struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS]; > struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; > @@ -573,6 +574,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, > int type, u64 parent_bus_addr, > u8 bar, size_t size); > void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); > +void dw_pcie_config_l1ss(struct dw_pcie *pci); > void dw_pcie_setup(struct dw_pcie *pci); > void dw_pcie_iatu_detect(struct dw_pcie *pci); > int dw_pcie_edma_detect(struct dw_pcie *pci); > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 805edbbfe7eb..61c2f4e2f74d 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1067,6 +1067,8 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val &= ~REQ_NOT_ENTR_L1; > writel(val, pcie->parf + PARF_PM_CTRL); > > + pci->l1ss_support = true; > + > val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > val |= EN; > writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 10e74458e667..3934757baa30 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -703,6 +703,9 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) > val |= (pcie->aspm_pwr_on_t << 19); > dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); > > + if (pcie->supports_clkreq) > + pci->l1ss_support = true; > + > /* Program L0s and L1 entrance latencies */ > val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); > val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;