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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-842828836efsm17689182b3a.38.2026.06.08.04.45.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 04:45:14 -0700 (PDT) Message-ID: <79e704ef-bcaa-456c-9d0a-0680bd885563@gmail.com> Date: Mon, 8 Jun 2026 19:45:10 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller support To: Mark Brown Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260608025009.1504971-1-cwweng@nuvoton.com> <20260608025009.1504971-3-cwweng@nuvoton.com> <8e751df3-6237-4c8e-9c87-34bb67e435f7@sirena.org.uk> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <8e751df3-6237-4c8e-9c87-34bb67e435f7@sirena.org.uk> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260608_044519_373994_E45865A1 X-CRM114-Status: GOOD ( 11.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mark, Thanks for the review. I will add mem_caps in v3 and set per_op_freq for the spi-mem path. I will keep the direct CS polarity handling for now, and also add SPI_CS_HIGH to mode_bits. I understand that moving this handling into the core would be a separate issue. Best regards, Chi-Wen Mark Brown 於 2026/6/8 下午 06:53 寫道: > On Mon, Jun 08, 2026 at 10:50:09AM +0800, Chi-Wen Weng wrote: >> Add SPI controller driver support for the Nuvoton MA35D1 Quad SPI >> controller. >> +static void nuvoton_qspi_mem_set_cs(struct spi_device *spi, bool enable) >> +{ >> + struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); >> + bool assert = enable; >> + >> + if (spi->mode & SPI_CS_HIGH) >> + assert = !assert; > Hrm, we should have the core deal with this. Separate issue though. > >> + ctlr->num_chipselect = NUVOTON_QSPI_DEFAULT_NUM_CS; >> + ctlr->mem_ops = &nuvoton_qspi_mem_ops; > We don't specify mem_caps, I'm vaugely surprised nothing trips over that > when testing.