From: John Garry <john.g.garry@oracle.com>
To: Jing Zhang <renyu.zj@linux.alibaba.com>,
Ian Rogers <irogers@google.com>,
Xing Zhengjun <zhengjun.xing@linux.intel.com>,
Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>,
Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Andrew Kilroy <andrew.kilroy@arm.com>,
Shuai Xue <xueshuai@linux.alibaba.com>,
Zhuo Song <zhuo.song@linux.alibaba.com>
Subject: Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2
Date: Wed, 4 Jan 2023 17:26:19 +0000 [thread overview]
Message-ID: <7aa225df-af25-a6be-9bef-c965488ba43a@oracle.com> (raw)
In-Reply-To: <1f3d53cb-4160-e29d-3934-d6a488d9fd49@linux.alibaba.com>
On 04/01/2023 05:05, Jing Zhang wrote:
>
>
> 在 2023/1/3 下午7:52, John Garry 写道:
>> On 03/01/2023 11:39, Jing Zhang wrote:
>>> The formula of topdown L1 on neoverse-n2 is from ARM sbsa7.0 platform
>>> design document [0], D37-38.
>>
>> I think that I mentioned this before - if the these metrics are coming from an sbsa doc, then they are standard. As such, we can make them "arch std events" and put them in a common json such as sbsa.json, so that other cores may reuse.
>>
>> You don't strictly have to do do this now, but it would be better.
>>
>
> Hi John,
Hi Jing,
>
> I would really like to do this, but as discussed earlier, slot is different on each architectures.
> If I do not specify the value of the slot in sbsa.json, then in the json file of n2/v1, I need to
> overwrite each topdown "MetricExpr". In other words, the metrics placed in the sbsa.json file only
> reuse "BriefDescription", "MetricGroup" and "ScaleUnit". So I'm not sure if it's acceptable?
I don't see a lot of value in that really.
However, for this value of slot, isn't this discoverable from a system
register per core? Quoting the sbsa: "The IMPLEMENTATION DEFINED
constant SLOTS is discoverable from the system register
PMMIR_EL1.SLOTS." Did you consider how this could be used?
>
> In addition, James mentioned that if the units and names and group names of different architectures
> are not unified, it will become complicated.
>
Thanks,
John
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next prev parent reply other threads:[~2023-01-04 17:30 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-03 11:39 [PATCH v5 0/6] Add metrics for neoverse-n2 Jing Zhang
2023-01-03 11:39 ` [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 " Jing Zhang
2023-01-03 11:52 ` John Garry
2023-01-04 5:05 ` Jing Zhang
2023-01-04 17:26 ` John Garry [this message]
2023-01-05 10:05 ` Jing Zhang
2023-01-05 10:13 ` John Garry
2023-01-05 11:02 ` Jing Zhang
2023-01-05 21:13 ` Ian Rogers
2023-01-06 10:14 ` John Garry
2023-01-06 10:34 ` Jing Zhang
2023-01-09 15:34 ` James Clark
2023-01-11 6:14 ` Ian Rogers
2023-01-03 11:39 ` [PATCH v5 2/6] perf vendor events arm64: Add TLB " Jing Zhang
2023-01-03 17:14 ` Ian Rogers
2023-01-04 5:21 ` Jing Zhang
2023-01-04 8:40 ` Jing Zhang
2023-01-04 16:57 ` Ian Rogers
2023-01-03 11:39 ` [PATCH v5 3/6] perf vendor events arm64: Add cache " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 4/6] perf vendor events arm64: Add branch " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 5/6] perf vendor events arm64: Add PE utilization " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 6/6] perf vendor events arm64: Add instruction mix " Jing Zhang
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