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Thu, 12 Jun 2025 01:42:41 -0700 (PDT) Received: from [192.168.1.3] ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a5619ab86dsm1296971f8f.44.2025.06.12.01.42.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jun 2025 01:42:40 -0700 (PDT) Message-ID: <7b080e97-375d-4521-b167-d0c4256dc464@linaro.org> Date: Thu, 12 Jun 2025 09:42:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/10] perf: arm_spe: Support FEAT_SPEv1p4 filters To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , leo.yan@arm.com References: <20250605-james-perf-feat_spe_eft-v3-0-71b0c9f98093@linaro.org> <20250605-james-perf-feat_spe_eft-v3-2-71b0c9f98093@linaro.org> <10f63976-afa7-4e1c-bec1-d9f2447d9c13@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <10f63976-afa7-4e1c-bec1-d9f2447d9c13@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250612_014243_130416_F5ED6789 X-CRM114-Status: GOOD ( 25.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/06/2025 8:35 am, Anshuman Khandual wrote: > On 05/06/25 4:19 PM, James Clark wrote: >> FEAT_SPEv1p4 (optional from Armv8.8) adds some new filter bits, so >> remove them from the previous version's RES0 bits using >> PMSEVFR_EL1_RES0_V1P4_EXCL. It also makes some previously available bits >> unavailable again, so add those back using PMSEVFR_EL1_RES0_V1P4_INCL. > > Just wondering - why cannot all the new applicable filter bits be added > explicitly for PMSEVFR_EL1_RES0_V1P4 without using exclude and include > intermediaries. > They could but there would be a lot of duplication. Each version tended to add only a few bits to the previous version. Also for consistency, they were already defined in this way. I didn't think there was much to gain by redefining the whole bitset just for this one, it's probably going to look just as messy. >> E.g: >> >> E[30], bit [30] >> When FEAT_SPEv1p4 is _not_ implemented ... >> >> FEAT_SPE_V1P3 has the same filters as V1P2 so explicitly add it to the >> switch. > A small nit - should FEAT_SPE_V1P3 addition be done in a previous patch > as it is an already existing thing ? > It's related to this patch because I change the default case. Before V1P3 hits 'default:' and returns PMSEVFR_EL1_RES0_V1P2. But now the highest supported is PMSEVFR_EL1_RES0_V1P4 for the default case so I need to add a case for V1P3 to keep it returning PMSEVFR_EL1_RES0_V1P2 filters. There's no bug. >> >> Reviewed-by: Leo Yan >> Tested-by: Leo Yan >> Signed-off-by: James Clark >> --- >> arch/arm64/include/asm/sysreg.h | 7 +++++++ >> drivers/perf/arm_spe_pmu.c | 5 ++++- >> 2 files changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index f1bb0d10c39a..880090df3efc 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -358,6 +358,13 @@ >> (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) >> #define PMSEVFR_EL1_RES0_V1P2 \ >> (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) >> +#define PMSEVFR_EL1_RES0_V1P4_EXCL \ >> + (BIT_ULL(2) | BIT_ULL(4) | GENMASK_ULL(10, 8) | GENMASK_ULL(23, 19)) >> +#define PMSEVFR_EL1_RES0_V1P4_INCL \ >> + (GENMASK_ULL(31, 26))> +#define PMSEVFR_EL1_RES0_V1P4 \ >> + (PMSEVFR_EL1_RES0_V1P4_INCL | \ >> + (PMSEVFR_EL1_RES0_V1P2 & ~PMSEVFR_EL1_RES0_V1P4_EXCL)) >> >> /* Buffer error reporting */ >> #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT >> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c >> index 3efed8839a4e..d9f6d229dce8 100644 >> --- a/drivers/perf/arm_spe_pmu.c >> +++ b/drivers/perf/arm_spe_pmu.c >> @@ -701,9 +701,12 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) >> case ID_AA64DFR0_EL1_PMSVer_V1P1: >> return PMSEVFR_EL1_RES0_V1P1; >> case ID_AA64DFR0_EL1_PMSVer_V1P2: >> + case ID_AA64DFR0_EL1_PMSVer_V1P3: >> + return PMSEVFR_EL1_RES0_V1P2; >> + case ID_AA64DFR0_EL1_PMSVer_V1P4: >> /* Return the highest version we support in default */ >> default: >> - return PMSEVFR_EL1_RES0_V1P2; >> + return PMSEVFR_EL1_RES0_V1P4; >> } >> } >> >> > > > >