From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 474CFC7115E for ; Thu, 29 Aug 2024 03:40:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=n+Lh2vHxUB+86yeUS0d5uwMJVWzCawU4cjiNowF9hs4=; b=yBN0RmEOnqboT55CRs3OIxmnA2 zbpC9/95rDstIG986/96165bhut5bUBz0VCR7iJ9MWhgVLQkkRG1sgjP5r4b12hw6OhRpdpO5xSuA StQlRj9/qOmvrlLMiv9mKvU1fsd6WUoAa986fzB8rS078jclez0dAjOmgaYA+MGJ2r21EWEeMlXTN HI8acHuR44uYh0TQ2cP61JTIn/5PCOQdAO7HgLR1f8Mrt9Odiu0pFCS4S3IbayspCUlf7VFbV9zkJ O5qnyOnNbUlmf6/AuYF5SkhV8o9mCjDoHUtGm4DdxZzuj01Ie5fYz+GKDlK94g6/UfpiJ0nyrTTGb DEs8EWdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sjW19-00000000O7S-10V8; Thu, 29 Aug 2024 03:40:15 +0000 Received: from out-171.mta0.migadu.com ([91.218.175.171]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sjW0H-00000000Nt7-1K6G for linux-arm-kernel@lists.infradead.org; Thu, 29 Aug 2024 03:39:23 +0000 Message-ID: <7c2237bd-c1eb-4cf6-9135-420a321ebd3b@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1724902758; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n+Lh2vHxUB+86yeUS0d5uwMJVWzCawU4cjiNowF9hs4=; b=RKYCS/bs9Fuf2a0LIc6oZEc0Qxnsqv4A/6jg2vqw9A1X/vYr6M0gINoQ8cYiZo68t/9AW/ 7hTk0h0Q3vTIPdKJW1u/PDgjvwFtRiTbiKd6SkCPS50ico497y8yK/zh+jlcuEuMRbqZOL GN5HEvWBmr2PiMol50Z18Xh9PnBmcMA= Date: Thu, 29 Aug 2024 11:39:09 +0800 MIME-Version: 1.0 Subject: Re: [PATCH v2 02/14] arm: adjust_pte() use pte_offset_map_rw_nolock() To: David Hildenbrand , Qi Zheng Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, hughd@google.com, willy@infradead.org, vbabka@kernel.org, akpm@linux-foundation.org, rppt@kernel.org, vishal.moola@gmail.com, peterx@redhat.com, ryan.roberts@arm.com, christophe.leroy2@cs-soprasteria.com References: <7915acf5887e7bf0c5cc71ff30ad2fe8447d005d.1724310149.git.zhengqi.arch@bytedance.com> <77f3f5ce-dd12-4ca2-90cd-0f2226fe26ba@redhat.com> X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Muchun Song In-Reply-To: <77f3f5ce-dd12-4ca2-90cd-0f2226fe26ba@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240828_203921_935355_433C8A9B X-CRM114-Status: GOOD ( 20.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2024/8/26 23:26, David Hildenbrand wrote: > On 22.08.24 09:13, Qi Zheng wrote: >> In do_adjust_pte(), we may modify the pte entry. At this time, the write >> lock of mmap_lock is not held, and the pte_same() check is not performed >> after the PTL held. The corresponding pmd entry may have been modified >> concurrently. Therefore, in order to ensure the stability if pmd entry, >> use pte_offset_map_rw_nolock() to replace pte_offset_map_nolock(), >> and do >> pmd_same() check after holding the PTL. >> >> Signed-off-by: Qi Zheng Reviewed-by: Muchun Song >> --- >>   arch/arm/mm/fault-armv.c | 9 ++++++++- >>   1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c >> index 831793cd6ff94..de6c7d8a2ddfc 100644 >> --- a/arch/arm/mm/fault-armv.c >> +++ b/arch/arm/mm/fault-armv.c >> @@ -94,6 +94,7 @@ static int adjust_pte(struct vm_area_struct *vma, >> unsigned long address, >>       pud_t *pud; >>       pmd_t *pmd; >>       pte_t *pte; >> +    pmd_t pmdval; >>       int ret; >>         pgd = pgd_offset(vma->vm_mm, address); >> @@ -112,16 +113,22 @@ static int adjust_pte(struct vm_area_struct >> *vma, unsigned long address, >>       if (pmd_none_or_clear_bad(pmd)) >>           return 0; >>   +again: >>       /* >>        * This is called while another page table is mapped, so we >>        * must use the nested version.  This also means we need to >>        * open-code the spin-locking. >>        */ >> -    pte = pte_offset_map_nolock(vma->vm_mm, pmd, address, &ptl); >> +    pte = pte_offset_map_rw_nolock(vma->vm_mm, pmd, address, >> &pmdval, &ptl); >>       if (!pte) >>           return 0; >>         do_pte_lock(ptl); >> +    if (unlikely(!pmd_same(pmdval, pmdp_get_lockless(pmd)))) { >> +        do_pte_unlock(ptl); >> +        pte_unmap(pte); >> +        goto again; >> +    } >>         ret = do_adjust_pte(vma, address, pfn, pte); > > Looks correct to me, but I wonder why the missing pmd_same check is > not an issue so far ... any experts? THP on __LINUX_ARM_ARCH__ < 6 is > not really used/possible? I think it is because it does not support THP. TRANSPARENT_HUGEPAGE depends on HAVE_ARCH_TRANSPARENT_HUGEPAGE which depends on ARM_LPAE. However, the Kconfig says ARM_LPAE is only supported on ARMv7 processor. config ARM_LPAE          bool "Support for the Large Physical Address Extension"          depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \                  !CPU_32v4 && !CPU_32v3          select PHYS_ADDR_T_64BIT          select SWIOTLB          help            Say Y if you have an ARMv7 processor supporting the LPAE page            table format and you would like to access memory beyond the            4GB limit. The resulting kernel image will not run on            processors without the LPA extension.            If unsure, say N. Thanks. > > Acked-by: David Hildenbrand >