From: Xianwei Zhao <xianwei.zhao@amlogic.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] arm64: dts: amlogic: Add S6 Reset Controller
Date: Fri, 19 Dec 2025 10:46:16 +0800 [thread overview]
Message-ID: <7d6084d2-3c56-43b8-8337-0b696614e4fb@amlogic.com> (raw)
In-Reply-To: <CAFBinCA19ws1OmfZLh+OSmiEuvY4owOKyzFpaz5KO6E8HaKmmg@mail.gmail.com>
Hi Martin,
Thanks for your reply.
On 2025/12/17 23:51, Martin Blumenstingl wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Nov 27, 2025 at 8:30 AM Xianwei Zhao via B4 Relay
> <devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
> [...]
>> +#define RESET_BRG_MAIL_DMC_PIPEL 167
> On the S7 SoC this reset line is called RESET_BRG_MALI_PIPL0:
> - is MAIL <> MALI a typo (seems like it should be MALI)?
Yes. I will fix it.
> - and is PIPEL <> PIPL also a typo (I don't know which one is "correct")?
PIPEL is PIPE , I will fix it.
next prev parent reply other threads:[~2025-12-19 2:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-27 7:30 [PATCH 0/4] Add support for Amlogic S6/S7/S7D Reset Xianwei Zhao via B4 Relay
2025-11-27 7:30 ` [PATCH 1/4] dt-bindings: reset: Add compatible for Amlogic S6/S7/S7D Xianwei Zhao via B4 Relay
2025-11-27 17:30 ` Conor Dooley
2025-11-27 7:30 ` [PATCH 2/4] arm64: dts: amlogic: Add S6 Reset Controller Xianwei Zhao via B4 Relay
2025-12-17 15:51 ` Martin Blumenstingl
2025-12-19 2:46 ` Xianwei Zhao [this message]
2025-11-27 7:30 ` [PATCH 3/4] arm64: dts: amlogic: Add S7 " Xianwei Zhao via B4 Relay
2025-11-27 7:30 ` [PATCH 4/4] arm64: dts: amlogic: Add S7D " Xianwei Zhao via B4 Relay
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