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Thu, 27 Nov 2025 08:06:04 -0800 (PST) Received: from [192.168.1.3] ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4790ab8bb21sm107834545e9.0.2025.11.27.08.06.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Nov 2025 08:06:04 -0800 (PST) Message-ID: <7dadacee-b95d-49a2-88b0-73367dab25ed@linaro.org> Date: Thu, 27 Nov 2025 16:06:03 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/9] KVM: arm64: Fix Trace Buffer trap polarity for protected VMs To: Fuad Tabba Cc: Marc Zyngier , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com References: <20251118103807.707500-1-tabba@google.com> <20251118103807.707500-3-tabba@google.com> <868qftqehe.wl-maz@kernel.org> <865xaxqal2.wl-maz@kernel.org> <7f1c187b-0f94-49c5-b4c9-2f414ab0ac8a@linaro.org> Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251127_080606_992688_1B9EFF9C X-CRM114-Status: GOOD ( 22.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 27/11/2025 3:38 pm, Fuad Tabba wrote: > On Thu, 27 Nov 2025 at 15:26, James Clark wrote: >> >> >> >> On 26/11/2025 11:48 am, Fuad Tabba wrote: >>> On Wed, 26 Nov 2025 at 11:47, Marc Zyngier wrote: >>>> >>>> On Wed, 26 Nov 2025 10:37:57 +0000, >>>> Fuad Tabba wrote: >>>>> >>>>> Hi Marc, >>>>> >>>>> On Wed, 26 Nov 2025 at 10:23, Marc Zyngier wrote: >>>>>> >>>>>> On Tue, 18 Nov 2025 10:37:59 +0000, >>>>>> Fuad Tabba wrote: >>>>>>> >>>>>>> The E2TB bits in MDCR_EL2 control trapping of Trace Buffer system >>>>>>> register accesses. These accesses are trapped to EL2 when the bits are >>>>>>> clear. >>>>>>> >>>>>>> The trap initialization logic for protected VMs in pvm_init_traps_mdcr() >>>>>>> had the polarity inverted. When a guest did not support the Trace Buffer >>>>>>> feature, the code was setting E2TB. This incorrectly disabled the trap, >>>>>>> potentially allowing a protected guest to access registers for a feature >>>>>>> it was not given. >>>>>>> >>>>>>> Fix this by inverting the operation. >>>>>>> >>>>>>> Fixes: f50758260bff ("KVM: arm64: Group setting traps for protected VMs by control register") >>>>>>> Signed-off-by: Fuad Tabba >>>>>>> --- >>>>>>> arch/arm64/kvm/hyp/nvhe/pkvm.c | 2 +- >>>>>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>>>>> >>>>>>> diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c >>>>>>> index 8d06a246dfd1..f6f8996c4f97 100644 >>>>>>> --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c >>>>>>> +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c >>>>>>> @@ -118,7 +118,7 @@ static void pvm_init_traps_mdcr(struct kvm_vcpu *vcpu) >>>>>>> val |= MDCR_EL2_TTRF; >>>>>>> >>>>>>> if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, IMP)) >>>>>>> - val |= MDCR_EL2_E2TB_MASK; >>>>>>> + val &= ~MDCR_EL2_E2TB_MASK; >>>>>> >>>>>> This does not only change the trapping logic (bit 24). It also change >>>>>> the ownership of the buffer (bit 25). I wonder whether you should do >>>>>> something for that, maybe by clearing TRBLIMITR_EL1.E, because >>>>>> otherwise, you keep tracing, but using an EL2 VA. What could possibly >>>>>> go wrong? >>>>>> >>>>>> Overall, I'm very uneasy about TRBE in the context of pKVM. >>>>> >>>>> So should we clear/restore TRBLIMITR_EL1.E on guest entry/exit in >>>>> protected mode? >>>> >>>> I think you need something of the sort, yes. Overall, SPE and TRBE >>>> should be aligned on what they are allowed to do, as they are two >>>> sides of the same ugly coin. >>> >>> I'll fix this (or add a patch to do this, depending on how it looks) >>> when I respin. >>> >>> Cheers, >>> /fuad >>> >> >> To understand this, is it just belt-and-braces because you don't trust >> the current filter clearing in TRFCR_EL1? And to reduce the potential >> for mistakes leading to trace leakages? I suppose even the hardware >> itself could have some errata where it tries to access the buffer, even >> if we've completely filtered out trace and flushed before going into the >> guest. > > Yes, we don't trust the host. The pKVM threat model is to protect > against a malicious host. > > Getting into hardware errata... that's a can of worms. I haven't > considered that. > > Cheers, > /fuad > > But the hypervisor already clears the filters, equivalent to clearing TRBLIMITR_EL1.E. Which is why I was wondering if there was something extra on top of the model where the host isn't trusted. I would assume that without anything more specific that just clearing the filters is enough. If we trust the hardware then it is anyway. >> Thanks >> James >> >>>> M. >>>> >>>> -- >>>> Without deviation from the norm, progress is not possible. >>> >>