Re: [PATCH v2 2/5] arm64: dts: imx8qxp: Add display controller subsystem

[Liu Ying <victor.liu@nxp.com>]

On Fri, Oct 16, 2026 at 02:46:47PM +0200, Alexander Stein wrote:
> Hi,

Hi Alexander,

> 
> Am Donnerstag, 15. Oktober 2026, 05:41:54 Mitteleuropäische Sommerzeit schrieb Liu Ying:
>> Hi Alexander,
>>
>> On Wed, Oct 14, 2026 at 09:16:46AM +0200, Alexander Stein wrote:
>>
>> [...]
>>
>>> +	dc0: display-controller@56180000 {
>>> +		reg = <0x56180000 0x40000>;
>>> +		clocks = <&dc0_lpcg IMX_LPCG_CLK_4>;
>>> +		power-domains = <&pd IMX_SC_R_DC_0>;
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +		ranges;
>>> +		status = "disabled";
>>> +
>>> +		dc0_intc: interrupt-controller@56180040 {
>>> +			reg = <0x56180040 0x60>;
>>> +			clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
>>> +			interrupt-controller;
>>> +			interrupt-parent = <&dc0_irqsteer>;
>>> +			#interrupt-cells = <1>;
>>> +			interrupts = <448>, <449>, <450>,  <64>,
>>> +				      <65>,  <66>,  <67>,  <68>,
>>> +				      <69>,  <70>, <193>, <194>,
>>> +				     <195>, <196>, <197>,  <72>,
>>> +				      <73>,  <74>,  <75>,  <76>,
>>> +				      <77>,  <78>,  <79>,  <80>,
>>> +				      <81>, <199>, <200>, <201>,
>>> +				     <202>, <203>, <204>, <205>,
>>> +				     <206>, <207>, <208>,   <5>,
>>> +				       <0>,   <1>,   <2>,   <3>,
>>> +				       <4>,  <82>,  <83>,  <84>,
>>> +				      <85>, <209>, <210>, <211>,
>>> +				     <212>;
>>> +			interrupt-names = "store9_shdload",
>>> +					  "store9_framecomplete",
>>> +					  "store9_seqcomplete",
>>> +					  "extdst0_shdload",
>>> +					  "extdst0_framecomplete",
>>> +					  "extdst0_seqcomplete",
>>> +					  "extdst4_shdload",
>>> +					  "extdst4_framecomplete",
>>> +					  "extdst4_seqcomplete",
>>> +					  "extdst1_shdload",
>>> +					  "extdst1_framecomplete",
>>> +					  "extdst1_seqcomplete",
>>> +					  "extdst5_shdload",
>>> +					  "extdst5_framecomplete",
>>> +					  "extdst5_seqcomplete",
>>> +					  "disengcfg_shdload0",
>>> +					  "disengcfg_framecomplete0",
>>> +					  "disengcfg_seqcomplete0",
>>> +					  "framegen0_int0",
>>> +					  "framegen0_int1",
>>> +					  "framegen0_int2",
>>> +					  "framegen0_int3",
>>> +					  "sig0_shdload",
>>> +					  "sig0_valid",
>>> +					  "sig0_error",
>>> +					  "disengcfg_shdload1",
>>> +					  "disengcfg_framecomplete1",
>>> +					  "disengcfg_seqcomplete1",
>>> +					  "framegen1_int0",
>>> +					  "framegen1_int1",
>>> +					  "framegen1_int2",
>>> +					  "framegen1_int3",
>>> +					  "sig1_shdload",
>>> +					  "sig1_valid",
>>> +					  "sig1_error",
>>> +					  "reserved",
>>> +					  "cmdseq_error",
>>> +					  "comctrl_sw0",
>>> +					  "comctrl_sw1",
>>> +					  "comctrl_sw2",
>>> +					  "comctrl_sw3",
>>> +					  "framegen0_primsync_on",
>>> +					  "framegen0_primsync_off",
>>> +					  "framegen0_secsync_on",
>>> +					  "framegen0_secsync_off",
>>> +					  "framegen1_primsync_on",
>>> +					  "framegen1_primsync_off",
>>> +					  "framegen1_secsync_on",
>>> +					  "framegen1_secsync_off";
>>> +		};
>>> +
>>> +		dc0_pixel_engine: pixel-engine@56180800 {
>>> +			reg = <0x56180800 0xac00>;
>>> +			clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			ranges;
>>> +
>>> +			dc0_constframe0: constframe@56180960 {
>>> +				reg = <0x56180960 0xc>, <0x56184400 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_extdst0: extdst@56180980 {
>>> +				reg = <0x56180980 0x1c>, <0x56184800 0x28>;
>>> +				reg-names = "pec", "cfg";
>>> +				interrupt-parent = <&dc0_intc>;
>>> +				interrupts = <3>, <4>, <5>;
>>> +				interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +			};
>>> +
>>> +			dc0_constframe4: constframe@561809a0 {
>>> +				reg = <0x561809a0 0xc>, <0x56184c00 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_extdst4: extdst@561809c0 {
>>> +				reg = <0x561809c0 0x1c>, <0x56185000 0x28>;
>>> +				reg-names = "pec", "cfg";
>>> +				interrupt-parent = <&dc0_intc>;
>>> +				interrupts = <6>, <7>, <8>;
>>> +				interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +			};
>>> +
>>> +			dc0_constframe1: constframe@561809e0 {
>>> +				reg = <0x561809e0 0xc>, <0x56185400 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_extdst1: extdst@56180a00 {
>>> +				reg = <0x56180a00 0x1c>, <0x56185800 0x28>;
>>> +				reg-names = "pec", "cfg";
>>> +				interrupt-parent = <&dc0_intc>;
>>> +				interrupts = <9>, <10>, <11>;
>>> +				interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +			};
>>> +
>>> +			dc0_constframe5: constframe@56180a20 {
>>> +				reg = <0x56180a20 0xc>, <0x56185c00 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_extdst5: extdst@56180a40 {
>>> +				reg = <0x56180a40 0x1c>, <0x56186000 0x28>;
>>> +				reg-names = "pec", "cfg";
>>> +				interrupt-parent = <&dc0_intc>;
>>> +				interrupts = <12>, <13>, <14>;
>>> +				interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +			};
>>> +
>>> +			dc0_fetchwarp2: fetchwarp@56180a60 {
>>> +				reg = <0x56180a60 0x10>, <0x56186400 0x190>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_fetchlayer0: fetchlayer@56180ac0 {
>>> +				reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_layerblend0: layerblend@56180ba0 {
>>> +				reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_layerblend1: layerblend@56180bc0 {
>>> +				reg = <0x56180bc0 0x10>, <0x5618a800 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_layerblend2: layerblend@56180be0 {
>>> +				reg = <0x56180be0 0x10>, <0x5618ac00 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +
>>> +			dc0_layerblend3: layerblend@56180c00 {
>>> +				reg = <0x56180c00 0x10>, <0x5618b000 0x20>;
>>> +				reg-names = "pec", "cfg";
>>> +			};
>>> +		};
>>> +
>>> +		dc0_display_engine0: display-engine@5618b400 {
>>> +			reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
>>> +			reg-names = "top", "cfg";
>>> +			interrupt-parent = <&dc0_intc>;
>>> +			interrupts = <15>, <16>, <17>;
>>> +			interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +			power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			ranges;
>>> +
>>> +			dc0_framegen0: framegen@5618b800 {
>>> +				reg = <0x5618b800 0x98>;
>>> +				clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
>>> +				interrupt-parent = <&dc0_intc>;
>>> +				interrupts = <18>, <19>, <20>, <21>,
>>> +					     <41>, <42>, <43>, <44>;
>>> +				interrupt-names = "int0", "int1", "int2", "int3",
>>> +						  "primsync_on", "primsync_off",
>>> +						  "secsync_on", "secsync_off";
>>> +			};
>>> +
>>> +			dc0_tcon0: tcon@5618c800 {
>>> +				reg = <0x5618c800 0x588>;
>>> +
>>> +				port {
>>> +					dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
>>> +						remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
>>> +					};
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		dc0_display_engine1: display-engine@5618b420 {
>>> +			reg = <0x5618b420 0x14>, <0x5618d400 0x1c00>;
>>> +			reg-names = "top", "cfg";
>>> +			interrupt-parent = <&dc0_intc>;
>>> +			interrupts = <25>, <26>, <27>;
>>> +			interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +			power-domains = <&pd IMX_SC_R_DC_0_PLL_1>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			ranges;
>>> +
>>> +			dc0_framegen1: framegen@5618d400 {
>>> +				reg = <0x5618d400 0x98>;
>>> +				clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_1>;
>>> +				interrupt-parent = <&dc0_intc>;
>>> +				interrupts = <28>, <29>, <30>, <31>,
>>> +					     <45>, <46>, <47>, <48>;
>>> +				interrupt-names = "int0", "int1", "int2", "int3",
>>> +						  "primsync_on", "primsync_off",
>>> +						  "secsync_on", "secsync_off";
>>> +			};
>>> +
>>> +			dc0_tcon1: tcon@5618e400 {
>>> +				reg = <0x5618e400 0x588>;
>>> +
>>> +				port {
>>> +					dc0_disp1_dc0_pixel_combiner_ch1: endpoint {
>>> +						remote-endpoint = <&dc0_pixel_combiner_ch1_dc0_disp1>;
>>> +					};
>>> +				};
>>> +			};
>>> +		};
>>> +	};
>>
>> I'm thinking that it would be good to have a complete display controller
>> DT node in the first place, including those prefetch engines attached to
>> fetchunits through the fsl,prg property.  In this way, display controller
>> driver's life would be easier - all child/grandchild devices are always
>> available.  I'm considering to adding a check to the Linux display controller
>> driver to ensure the availability(at least for critical child/grandchild
>> devices).
> 
> Well, this sounds reasonable, but this is beyond my knowledge about the
> internals of the display controller.
> FWIW it works (at least in my case), any additional DT node could be added
> later on.

If someone says that new kernel must support old device tree, then the display
driver's life would be not be easy.

> If there is something to test/review feel free to send it onto the
> list. Please keep me on CC.

I can try to CC you, but in case I forget to do so, the proper way for you
is to get any patch in question by yourself - lei + mutt is a typical solution.

> 
> Thanks and best regards
> Alexander

-- 
Regards,
Liu Ying