* [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile
@ 2025-07-14 14:06 Sirius Wang
2025-07-14 14:06 ` [PATCH v4 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Sirius Wang
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Sirius Wang @ 2025-07-14 14:06 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang
We add basic chip support for Mediatek MT8189 on evaluation board.
In this series, we also add dt-bindings document definition for MT8189.
This series is based on tag: next-20250714
Changs in v4:
- Correct cpu-idle-states
- Change the "reg" property name of the "memory" node in the
device tree source (DTS) to lowercase.
Changs in v3:
- Move ulposc and ulposc3 before cpu nodes.
- Refactor cpu-map to a single cluster0.
- Change cpu nodes name from medium core to big core.
- Move psci before timer nodes.
Changs in v2:
- Fix warning issues for make CHECK_DTBS=y
- Add mediatek,uart.yaml document
Sirius Wang (3):
dt-bindings: arm: Add compatible for MediaTek MT8189
dt-bindings: serial: mediatek,uart: Add compatible for MT8189
arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../bindings/serial/mediatek,uart.yaml | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 419 ++++++++++++++++++
5 files changed, 445 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
--
2.45.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189
2025-07-14 14:06 [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
@ 2025-07-14 14:06 ` Sirius Wang
2025-07-14 14:06 ` [PATCH v4 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 Sirius Wang
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Sirius Wang @ 2025-07-14 14:06 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang
This commit adds dt-binding documentation for the MediaTek MT8189
reference board.
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 19ed9448c9c2..5052b6b2dcce 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -382,6 +382,10 @@ properties:
- enum:
- mediatek,mt8188-evb
- const: mediatek,mt8188
+ - items:
+ - enum:
+ - mediatek,mt8189-evb
+ - const: mediatek,mt8189
- description: Google Hayato
items:
- const: google,hayato-rev1
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189
2025-07-14 14:06 [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
2025-07-14 14:06 ` [PATCH v4 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Sirius Wang
@ 2025-07-14 14:06 ` Sirius Wang
2025-07-14 14:06 ` [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Sirius Wang
2025-07-14 14:26 ` [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang (王皓昱)
3 siblings, 0 replies; 7+ messages in thread
From: Sirius Wang @ 2025-07-14 14:06 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang, Conor Dooley
Add compatible string for serial on MT8189 SoC.
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
index 5bd8a8853ae0..3f0f4aea0a4c 100644
--- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -47,6 +47,7 @@ properties:
- mediatek,mt8183-uart
- mediatek,mt8186-uart
- mediatek,mt8188-uart
+ - mediatek,mt8189-uart
- mediatek,mt8192-uart
- mediatek,mt8195-uart
- mediatek,mt8365-uart
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
2025-07-14 14:06 [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
2025-07-14 14:06 ` [PATCH v4 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Sirius Wang
2025-07-14 14:06 ` [PATCH v4 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 Sirius Wang
@ 2025-07-14 14:06 ` Sirius Wang
2025-07-14 14:50 ` AngeloGioacchino Del Regno
2025-07-14 14:26 ` [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang (王皓昱)
3 siblings, 1 reply; 7+ messages in thread
From: Sirius Wang @ 2025-07-14 14:06 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang
Add mt8189 dts evaluation board and Mafefile
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 419 ++++++++++++++++++++
3 files changed, 440 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index a4df4c21399e..52c5b799308e 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+ model = "MediaTek MT8189 evaluation board";
+ compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+ chosen: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..a484a40a036c
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "mediatek,mt8189";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ clk32k: oscillator-clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ clk13m: oscillator-clk13m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: oscillator-clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk104m: oscillator-clk104m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-mult = <4>;
+ clock-div = <1>;
+ clock-output-names = "clk104m";
+ };
+
+ ulposc: oscillator-ulposc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <520000000>;
+ clock-output-names = "ulposc";
+ };
+
+ ulposc3: oscillator-ulposc3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "ulposc3";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ core4 {
+ cpu = <&cpu4>;
+ };
+ core5 {
+ cpu = <&cpu5>;
+ };
+ core6 {
+ cpu = <&cpu6>;
+ };
+ core7 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <25>;
+ exit-latency-us = <57>;
+ min-residency-us = <5700>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <35>;
+ exit-latency-us = <82>;
+ min-residency-us = <1890>;
+ };
+
+ cpu_cluster_off_l: cpu-cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <57>;
+ exit-latency-us = <134>;
+ min-residency-us = <5700>;
+ };
+
+ cpu_cluster_off_b: cpu-cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <144>;
+ min-residency-us = <2460>;
+ };
+
+ cpu_mcusys_off_l: cpu-mcusys-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <863>;
+ exit-latency-us = <1237>;
+ min-residency-us = <5700>;
+ };
+
+ cpu_mcusys_off_b: cpu-mcusys-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <648>;
+ exit-latency-us = <1172>;
+ min-residency-us = <4570>;
+ };
+
+ cpu_system_vcore: cpu-system-vcore {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020100ff>;
+ local-timer-stop;
+ entry-latency-us = <2400>;
+ exit-latency-us = <4800>;
+ min-residency-us = <35200>;
+ };
+
+ cpu_s2idle: cpu-s2idle {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020180ff>;
+ local-timer-stop;
+ entry-latency-us = <10000>;
+ exit-latency-us = <10000>;
+ min-residency-us = <4294967295>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+ };
+
+ memory: memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0xc000000 0 0x40000>, /* distributor */
+ <0 0xc040000 0 0x200000>; /* redistributor */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+ };
+
+ uart0: serial@11001000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+ };
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile
2025-07-14 14:06 [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
` (2 preceding siblings ...)
2025-07-14 14:06 ` [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Sirius Wang
@ 2025-07-14 14:26 ` Sirius Wang (王皓昱)
3 siblings, 0 replies; 7+ messages in thread
From: Sirius Wang (王皓昱) @ 2025-07-14 14:26 UTC (permalink / raw)
To: gregkh@linuxfoundation.org, AngeloGioacchino Del Regno,
robh@kernel.org, krzk+dt@kernel.org, jirislaby@kernel.org,
Sean Wang, conor+dt@kernel.org, matthias.bgg@gmail.com
Cc: linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, wenst@chromium.org,
Xavier Chang (張獻文)
On Mon, 2025-07-14 at 22:06 +0800, Sirius Wang wrote:
> We add basic chip support for Mediatek MT8189 on evaluation board.
>
> In this series, we also add dt-bindings document definition for
> MT8189.
>
> This series is based on tag: next-20250714
>
> Changs in v4:
> - Correct cpu-idle-states
> - Change the "reg" property name of the "memory" node in the
> device tree source (DTS) to lowercase.
>
> Changs in v3:
> - Move ulposc and ulposc3 before cpu nodes.
> - Refactor cpu-map to a single cluster0.
> - Change cpu nodes name from medium core to big core.
> - Move psci before timer nodes.
>
> Changs in v2:
> - Fix warning issues for make CHECK_DTBS=y
> - Add mediatek,uart.yaml document
>
>
> Sirius Wang (3):
> dt-bindings: arm: Add compatible for MediaTek MT8189
> dt-bindings: serial: mediatek,uart: Add compatible for MT8189
> arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
>
> .../devicetree/bindings/arm/mediatek.yaml | 4 +
> .../bindings/serial/mediatek,uart.yaml | 1 +
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
> arch/arm64/boot/dts/mediatek/mt8189.dtsi | 419
> ++++++++++++++++++
> 5 files changed, 445 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
>
Dear maintainers and reviewers:
I apologize for inconvenience for sending the incorrect version of this
patchese.
I will correct the issue and submit the correct version of the patchs
as soon as possible.
Thank you for your understanding and patience.
Best regards,
Sirius
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
2025-07-14 14:06 ` [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Sirius Wang
@ 2025-07-14 14:50 ` AngeloGioacchino Del Regno
2025-07-15 12:07 ` Sirius Wang (王皓昱)
0 siblings, 1 reply; 7+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-07-14 14:50 UTC (permalink / raw)
To: Sirius Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang
Il 14/07/25 16:06, Sirius Wang ha scritto:
> Add mt8189 dts evaluation board and Mafefile
>
> Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
> arch/arm64/boot/dts/mediatek/mt8189.dtsi | 419 ++++++++++++++++++++
> 3 files changed, 440 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index a4df4c21399e..52c5b799308e 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> new file mode 100644
> index 000000000000..e5d9ce1b8e61
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2025 MediaTek Inc.
> + * Author: Sirius Wang <sirius.wang@mediatek.com>
> + */
> +/dts-v1/;
> +#include "mt8189.dtsi"
> +
> +/ {
> + model = "MediaTek MT8189 evaluation board";
> + compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
> +
> + chosen: chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> new file mode 100644
> index 000000000000..a484a40a036c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> @@ -0,0 +1,419 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "mediatek,mt8189";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + clk32k: oscillator-clk32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + clock-output-names = "clk32k";
> + };
> +
> + clk13m: oscillator-clk13m {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&clk26m>;
> + clock-mult = <1>;
> + clock-div = <2>;
> + clock-output-names = "clk13m";
> + };
> +
> + clk26m: oscillator-clk26m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk104m: oscillator-clk104m {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&clk26m>;
> + clock-mult = <4>;
> + clock-div = <1>;
> + clock-output-names = "clk104m";
> + };
> +
> + ulposc: oscillator-ulposc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <520000000>;
> + clock-output-names = "ulposc";
> + };
> +
> + ulposc3: oscillator-ulposc3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "ulposc3";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + capacity-dmips-mhz = <742>;
> + cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
> + i-cache-size = <32768>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <128>;
> + d-cache-size = <32768>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + performance-domains = <&performance 0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + capacity-dmips-mhz = <742>;
> + cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
> + i-cache-size = <32768>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <128>;
> + d-cache-size = <32768>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + performance-domains = <&performance 0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + capacity-dmips-mhz = <742>;
> + cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
> + i-cache-size = <32768>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <128>;
> + d-cache-size = <32768>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + performance-domains = <&performance 0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + capacity-dmips-mhz = <742>;
> + cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
> + i-cache-size = <32768>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <128>;
> + d-cache-size = <32768>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + performance-domains = <&performance 0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + capacity-dmips-mhz = <742>;
> + cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
> + i-cache-size = <32768>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <128>;
> + d-cache-size = <32768>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + performance-domains = <&performance 0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + capacity-dmips-mhz = <742>;
> + cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
> + i-cache-size = <32768>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <128>;
> + d-cache-size = <32768>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + performance-domains = <&performance 0>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a78";
> + reg = <0x600>;
> + enable-method = "psci";
> + clock-frequency = <3000000000>;
> + capacity-dmips-mhz = <958>;
> + cpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_1>;
> + performance-domains = <&performance 1>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a78";
> + reg = <0x700>;
> + enable-method = "psci";
> + clock-frequency = <3000000000>;
> + capacity-dmips-mhz = <958>;
> + cpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;
> + i-cache-size = <65536>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <65536>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_1>;
> + performance-domains = <&performance 1>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + core4 {
> + cpu = <&cpu4>;
> + };
> + core5 {
> + cpu = <&cpu5>;
> + };
> + core6 {
> + cpu = <&cpu6>;
> + };
> + core7 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + cpu_off_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010000>;
> + local-timer-stop;
> + entry-latency-us = <25>;
> + exit-latency-us = <57>;
> + min-residency-us = <5700>;
> + };
> +
> + cpu_off_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010000>;
> + local-timer-stop;
> + entry-latency-us = <35>;
> + exit-latency-us = <82>;
> + min-residency-us = <1890>;
> + };
> +
> + cpu_cluster_off_l: cpu-cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <57>;
> + exit-latency-us = <134>;
> + min-residency-us = <5700>;
> + };
> +
> + cpu_cluster_off_b: cpu-cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <144>;
> + min-residency-us = <2460>;
> + };
> +
> + cpu_mcusys_off_l: cpu-mcusys-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x02010007>;
> + local-timer-stop;
> + entry-latency-us = <863>;
> + exit-latency-us = <1237>;
> + min-residency-us = <5700>;
> + };
> +
> + cpu_mcusys_off_b: cpu-mcusys-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x02010007>;
> + local-timer-stop;
> + entry-latency-us = <648>;
> + exit-latency-us = <1172>;
> + min-residency-us = <4570>;
> + };
> +
> + cpu_system_vcore: cpu-system-vcore {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x020100ff>;
> + local-timer-stop;
> + entry-latency-us = <2400>;
> + exit-latency-us = <4800>;
> + min-residency-us = <35200>;
> + };
> +
> + cpu_s2idle: cpu-s2idle {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x020180ff>;
> + local-timer-stop;
> + entry-latency-us = <10000>;
> + exit-latency-us = <10000>;
> + min-residency-us = <4294967295>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <131072>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + next-level-cache = <&l3_0>;
> + cache-unified;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <262144>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + next-level-cache = <&l3_0>;
> + cache-unified;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <1048576>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + };
> + };
> +
> + memory: memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0xc0000000>;
The memory node is anyway filled in by the bootloader, so please just
/* The memory size is filled in by the bootloader */
reg = <0 0x40000000 0 0>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> +
> + performance: performance-controller@11bc10 {
> + compatible = "mediatek,cpufreq-hw";
> + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
> + #performance-domain-cells = <1>;
> + };
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0xc000000 0 0x40000>, /* distributor */
> + <0 0xc040000 0 0x200000>; /* redistributor */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
> + };
> +
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu6 &cpu7>;
> + };
> + };
> + };
> +
> + uart0: serial@11001000 {
> + compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
> + reg = <0 0x11001000 0 0x1000>;
> + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&clk26m>, <&clk26m>;
Instead of faking that clk26m, please just add the clock controller and use the
right clocks for this UART.
All of that is in its early stages and it doesn't make a lot of sense to start this
devicetree with just that - especially because, well, your target is to upstream
way more than that, right?
So just make it right - add the topckgen and infracfg_ao clocks and then just add
in all of the UART controllers with their CLK_INFRA_AO_UART(N) clock for an initial
devicetree.
Count that if you add the topckgen and infra_ao clocks, you'd be able to even add
the i2c, spi, mmc and others - but I will accept an initial devicetree with just
all of the UART controllers and without the extra busses for a start, there's no
problem with that. You can add those later if you wish.
Cheers,
Angelo
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
2025-07-14 14:50 ` AngeloGioacchino Del Regno
@ 2025-07-15 12:07 ` Sirius Wang (王皓昱)
0 siblings, 0 replies; 7+ messages in thread
From: Sirius Wang (王皓昱) @ 2025-07-15 12:07 UTC (permalink / raw)
To: gregkh@linuxfoundation.org, AngeloGioacchino Del Regno,
robh@kernel.org, krzk+dt@kernel.org, jirislaby@kernel.org,
Sean Wang, conor+dt@kernel.org, matthias.bgg@gmail.com
Cc: linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, wenst@chromium.org,
Xavier Chang (張獻文)
On Mon, 2025-07-14 at 16:50 +0200, AngeloGioacchino Del Regno wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Il 14/07/25 16:06, Sirius Wang ha scritto:
> > Add mt8189 dts evaluation board and Mafefile
> >
> > Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
> > arch/arm64/boot/dts/mediatek/mt8189.dtsi | 419
> > ++++++++++++++++++++
> > 3 files changed, 440 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index a4df4c21399e..52c5b799308e 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-
> > ciri-sku4.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > new file mode 100644
> > index 000000000000..e5d9ce1b8e61
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
> > @@ -0,0 +1,20 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2025 MediaTek Inc.
> > + * Author: Sirius Wang <sirius.wang@mediatek.com>
> > + */
> > +/dts-v1/;
> > +#include "mt8189.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT8189 evaluation board";
> > + compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
> > +
> > + chosen: chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > new file mode 100644
> > index 000000000000..a484a40a036c
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
> > @@ -0,0 +1,419 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt8189";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + clk32k: oscillator-clk32k {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32000>;
> > + clock-output-names = "clk32k";
> > + };
> > +
> > + clk13m: oscillator-clk13m {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&clk26m>;
> > + clock-mult = <1>;
> > + clock-div = <2>;
> > + clock-output-names = "clk13m";
> > + };
> > +
> > + clk26m: oscillator-clk26m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <26000000>;
> > + clock-output-names = "clk26m";
> > + };
> > +
> > + clk104m: oscillator-clk104m {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&clk26m>;
> > + clock-mult = <4>;
> > + clock-div = <1>;
> > + clock-output-names = "clk104m";
> > + };
> > +
> > + ulposc: oscillator-ulposc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <520000000>;
> > + clock-output-names = "ulposc";
> > + };
> > +
> > + ulposc3: oscillator-ulposc3 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <26000000>;
> > + clock-output-names = "ulposc3";
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x000>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + capacity-dmips-mhz = <742>;
> > + cpu-idle-states = <&cpu_off_l>,
> > <&cpu_s2idle>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_0>;
> > + performance-domains = <&performance 0>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu1: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x100>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + capacity-dmips-mhz = <742>;
> > + cpu-idle-states = <&cpu_off_l>,
> > <&cpu_s2idle>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_0>;
> > + performance-domains = <&performance 0>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x200>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + capacity-dmips-mhz = <742>;
> > + cpu-idle-states = <&cpu_off_l>,
> > <&cpu_s2idle>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_0>;
> > + performance-domains = <&performance 0>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu3: cpu@300 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x300>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + capacity-dmips-mhz = <742>;
> > + cpu-idle-states = <&cpu_off_l>,
> > <&cpu_s2idle>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_0>;
> > + performance-domains = <&performance 0>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu4: cpu@400 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x400>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + capacity-dmips-mhz = <742>;
> > + cpu-idle-states = <&cpu_off_l>,
> > <&cpu_s2idle>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_0>;
> > + performance-domains = <&performance 0>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu5: cpu@500 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55";
> > + reg = <0x500>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + capacity-dmips-mhz = <742>;
> > + cpu-idle-states = <&cpu_off_l>,
> > <&cpu_s2idle>;
> > + i-cache-size = <32768>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <128>;
> > + d-cache-size = <32768>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&l2_0>;
> > + performance-domains = <&performance 0>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu6: cpu@600 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a78";
> > + reg = <0x600>;
> > + enable-method = "psci";
> > + clock-frequency = <3000000000>;
> > + capacity-dmips-mhz = <958>;
> > + cpu-idle-states = <&cpu_off_b>,
> > <&cpu_s2idle>;
> > + i-cache-size = <65536>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <65536>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <256>;
> > + next-level-cache = <&l2_1>;
> > + performance-domains = <&performance 1>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu7: cpu@700 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a78";
> > + reg = <0x700>;
> > + enable-method = "psci";
> > + clock-frequency = <3000000000>;
> > + capacity-dmips-mhz = <958>;
> > + cpu-idle-states = <&cpu_off_b>,
> > <&cpu_s2idle>;
> > + i-cache-size = <65536>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <65536>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <256>;
> > + next-level-cache = <&l2_1>;
> > + performance-domains = <&performance 1>;
> > + #cooling-cells = <2>;
> > + };
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > + core2 {
> > + cpu = <&cpu2>;
> > + };
> > + core3 {
> > + cpu = <&cpu3>;
> > + };
> > + core4 {
> > + cpu = <&cpu4>;
> > + };
> > + core5 {
> > + cpu = <&cpu5>;
> > + };
> > + core6 {
> > + cpu = <&cpu6>;
> > + };
> > + core7 {
> > + cpu = <&cpu7>;
> > + };
> > + };
> > + };
> > +
> > + idle-states {
> > + entry-method = "psci";
> > +
> > + cpu_off_l: cpu-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x00010000>;
> > + local-timer-stop;
> > + entry-latency-us = <25>;
> > + exit-latency-us = <57>;
> > + min-residency-us = <5700>;
> > + };
> > +
> > + cpu_off_b: cpu-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x00010000>;
> > + local-timer-stop;
> > + entry-latency-us = <35>;
> > + exit-latency-us = <82>;
> > + min-residency-us = <1890>;
> > + };
> > +
> > + cpu_cluster_off_l: cpu-cluster-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <57>;
> > + exit-latency-us = <134>;
> > + min-residency-us = <5700>;
> > + };
> > +
> > + cpu_cluster_off_b: cpu-cluster-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <144>;
> > + min-residency-us = <2460>;
> > + };
> > +
> > + cpu_mcusys_off_l: cpu-mcusys-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x02010007>;
> > + local-timer-stop;
> > + entry-latency-us = <863>;
> > + exit-latency-us = <1237>;
> > + min-residency-us = <5700>;
> > + };
> > +
> > + cpu_mcusys_off_b: cpu-mcusys-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x02010007>;
> > + local-timer-stop;
> > + entry-latency-us = <648>;
> > + exit-latency-us = <1172>;
> > + min-residency-us = <4570>;
> > + };
> > +
> > + cpu_system_vcore: cpu-system-vcore {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x020100ff>;
> > + local-timer-stop;
> > + entry-latency-us = <2400>;
> > + exit-latency-us = <4800>;
> > + min-residency-us = <35200>;
> > + };
> > +
> > + cpu_s2idle: cpu-s2idle {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param =
> > <0x020180ff>;
> > + local-timer-stop;
> > + entry-latency-us = <10000>;
> > + exit-latency-us = <10000>;
> > + min-residency-us = <4294967295>;
> > + };
> > + };
> > +
> > + l2_0: l2-cache0 {
> > + compatible = "cache";
> > + cache-level = <2>;
> > + cache-size = <131072>;
> > + cache-line-size = <64>;
> > + cache-sets = <512>;
> > + next-level-cache = <&l3_0>;
> > + cache-unified;
> > + };
> > +
> > + l2_1: l2-cache1 {
> > + compatible = "cache";
> > + cache-level = <2>;
> > + cache-size = <262144>;
> > + cache-line-size = <64>;
> > + cache-sets = <512>;
> > + next-level-cache = <&l3_0>;
> > + cache-unified;
> > + };
> > +
> > + l3_0: l3-cache {
> > + compatible = "cache";
> > + cache-level = <3>;
> > + cache-size = <1048576>;
> > + cache-line-size = <64>;
> > + cache-sets = <2048>;
> > + cache-unified;
> > + };
> > + };
> > +
> > + memory: memory@40000000 {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0xc0000000>;
>
> The memory node is anyway filled in by the bootloader, so please just
>
> /* The memory size is filled in by the bootloader */
> reg = <0 0x40000000 0 0>;
>
I will fix it in next version.
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + timer: timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> > +
> > + performance: performance-controller@11bc10 {
> > + compatible = "mediatek,cpufreq-hw";
> > + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0
> > 0x120>;
> > + #performance-domain-cells = <1>;
> > + };
> > +
> > + gic: interrupt-controller@c000000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <4>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + reg = <0 0xc000000 0 0x40000>, /* distributor
> > */
> > + <0 0xc040000 0 0x200000>; /*
> > redistributor */
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +
> > + ppi-partitions {
> > + ppi_cluster0: interrupt-partition-0 {
> > + affinity = <&cpu0 &cpu1 &cpu2
> > &cpu3 &cpu4 &cpu5>;
> > + };
> > +
> > + ppi_cluster1: interrupt-partition-1 {
> > + affinity = <&cpu6 &cpu7>;
> > + };
> > + };
> > + };
> > +
> > + uart0: serial@11001000 {
> > + compatible = "mediatek,mt8189-uart",
> > "mediatek,mt6577-uart";
> > + reg = <0 0x11001000 0 0x1000>;
> > + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&clk26m>, <&clk26m>;
>
> Instead of faking that clk26m, please just add the clock controller
> and use the
> right clocks for this UART.
>
> All of that is in its early stages and it doesn't make a lot of sense
> to start this
> devicetree with just that - especially because, well, your target is
> to upstream
> way more than that, right?
>
> So just make it right - add the topckgen and infracfg_ao clocks and
> then just add
> in all of the UART controllers with their CLK_INFRA_AO_UART(N) clock
> for an initial
> devicetree.
>
> Count that if you add the topckgen and infra_ao clocks, you'd be able
> to even add
> the i2c, spi, mmc and others - but I will accept an initial
> devicetree with just
> all of the UART controllers and without the extra busses for a start,
> there's no
> problem with that. You can add those later if you wish.
>
> Cheers,
> Angelo
Thanks for your comments,
Since our clk driver will be submitted in a separate patch to address
this part, we are temporarily using a fake clk in this base version.
This approach enables other drivers to be upstreamed together and
includes the Makefile to allow code compilation.
We plan to submit the driver source code , DTS, and dt-bindings
together in the upcoming patch series.
>
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > + };
> > +};
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-07-15 12:57 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2025-07-14 14:06 [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
2025-07-14 14:06 ` [PATCH v4 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Sirius Wang
2025-07-14 14:06 ` [PATCH v4 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 Sirius Wang
2025-07-14 14:06 ` [PATCH v4 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Sirius Wang
2025-07-14 14:50 ` AngeloGioacchino Del Regno
2025-07-15 12:07 ` Sirius Wang (王皓昱)
2025-07-14 14:26 ` [PATCH v4 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang (王皓昱)
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