From: Kevin Hilman <khilman@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
p.zabel@pengutronix.de, linux-amlogic@lists.infradead.org
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com
Subject: Re: [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs
Date: Mon, 09 Dec 2019 14:25:57 -0800 [thread overview]
Message-ID: <7h5ziprv9m.fsf@baylibre.com> (raw)
In-Reply-To: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> According to the public S805 datasheet the RESET2 register uses the
> following bits for the PIC_DC, PSC and NAND reset lines:
> - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
> - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
> - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
>
> Update the reset IDs of these three reset lines so they don't conflict
> with PIC_DC and map to the actual hardware reset lines.
>
> Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Queued as a fix for v5.5-rc,
Thanks,
Kevin
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prev parent reply other threads:[~2019-12-09 22:26 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-30 18:53 [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs Martin Blumenstingl
2019-12-09 22:25 ` Kevin Hilman [this message]
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