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From: khilman@baylibre.com (Kevin Hilman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/2] update the L2 cache settings on Meson8/Meson8b
Date: Wed, 06 Dec 2017 11:44:48 -0800	[thread overview]
Message-ID: <7ha7yvsksv.fsf@baylibre.com> (raw)
In-Reply-To: <20171031222316.24548-1-martin.blumenstingl@googlemail.com> (Martin Blumenstingl's message of "Tue, 31 Oct 2017 23:23:14 +0100")

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> The L2 cache settings on our mainline kernel did not match the
> configuration from Amlogic's vendor kernel.
>
> This was boot-tested on a Meson8 (actually Meson8m2, but both use
> the same CPU cores and L2 cache configuration) and a Meson8b board.

Boot tested on meson8b-odroidc1, and applied to v4.16/dt,

Thanks,

Kevin

      parent reply	other threads:[~2017-12-06 19:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-31 22:23 [PATCH 0/2] update the L2 cache settings on Meson8/Meson8b Martin Blumenstingl
2017-10-31 22:23 ` [PATCH 1/2] ARM: dts: meson8b: add more L2 cache settings Martin Blumenstingl
2017-10-31 22:23 ` [PATCH 2/2] ARM: dts: meson8: " Martin Blumenstingl
2017-12-06 19:44 ` Kevin Hilman [this message]

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