[PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node

[PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node

[Martin Blumenstingl]

All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index eadb0832bcfc..7649dd1e0b9e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,13 +11,6 @@ / {
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
-	L2: cache-controller@c4200000 {
-		compatible = "arm,pl310-cache";
-		reg = <0xc4200000 0x1000>;
-		cache-unified;
-		cache-level = <2>;
-	};
-
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -172,6 +165,13 @@ timer_abcde: timer@9940 {
 			};
 		};
 
+		L2: cache-controller@c4200000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xc4200000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
 		periph: bus@c4300000 {
 			compatible = "simple-bus";
 			reg = <0xc4300000 0x10000>;
-- 
2.28.0


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Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node

[Kevin Hilman]

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Boot tested on meson8b-odroidc1

Tested-by: Kevin Hilman <khilman@baylibre.com>

Queuing for v5.10.

Thanks,

Kevin

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Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node

[Kevin Hilman]

On Sat, 15 Aug 2020 20:22:23 +0200, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.

Applied, thanks!

[1/1] ARM: dts: meson: move the L2 cache-controller inside the SoC node
      commit: 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0

Best regards,
-- 
Kevin Hilman <khilman@baylibre.com>

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