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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id h22sm4217098pgn.78.2019.11.21.15.46.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Nov 2019 15:46:10 -0800 (PST) From: Kevin Hilman To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Subject: Re: [PATCH] ARM: dts: meson8: fix the size of the PMU registers In-Reply-To: <20191117154154.170960-1-martin.blumenstingl@googlemail.com> References: <20191117154154.170960-1-martin.blumenstingl@googlemail.com> Date: Thu, 21 Nov 2019 15:46:09 -0800 Message-ID: <7hlfs8n67y.fsf@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191121_154611_846936_E3C5ABE2 X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Martin Blumenstingl writes: > The PMU registers are at least 0x18 bytes wide. Meson8b already uses a > size of 0x18. The structure of the PMU registers on Meson8 and Meson8b > is similar but not identical. > > Meson8 and Meson8b have the following registers in common (starting at > AOBUS + 0xe0): > #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) > #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) > #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) > #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) > > Meson8b additionally has these three registers: > #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) > #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) > #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) > > Thus we can assume that the register size of the PMU IP blocks is > identical on both SoCs (and Meson8 just contains some reserved registers > in that area) because the CEC registers start right after the PMU > (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). > > The upcoming power domain driver will need to read and write the > AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated > size is needed for that driver to work. > > Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") > Signed-off-by: Martin Blumenstingl Queued as a fix for v5.5-rc, Kevin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel