From: Kevin Hilman <khilman@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-amlogic@lists.infradead.org, ingrassia@epigenesys.com
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-arm-kernel@lists.infradead.org, jianxin.pan@amlogic.com,
linus.luessing@c0d3.blue
Subject: Re: [PATCH v3 2/2] ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins
Date: Thu, 10 Jan 2019 17:09:47 -0800 [thread overview]
Message-ID: <7hwoncov8k.fsf@baylibre.com> (raw)
In-Reply-To: <20181229143556.27339-3-martin.blumenstingl@googlemail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> According to the Odroid-C1+ schematics the Ethernet TXD1 signal is
> routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6.
> The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and
> TXD1 can be routed to DIF_2_N instead.
>
> The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both
> configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the
> same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured
> as TXD0 and TXD1 data lines as well.
> This results in a bad Ethernet receive performance. Presumably this is
> due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins.
> As a result of that data can only be transmitted on eth_txd2 and
> eth_txd3. However, I have no scope to fully confirm this assumption.
>
> The vendor u-boot sources for Odroid-C1 use the following Ethernet
> pinmux configuration:
> SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f);
> SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000);
> This translates to the following pin groups in the mainline kernel:
> - register 6 bit 0: eth_rxd1 (DIF_0_P)
> - register 6 bit 1: eth_rxd0 (DIF_0_N)
> - register 6 bit 2: eth_rx_dv (DIF_1_P)
> - register 6 bit 3: eth_rx_clk (DIF_1_N)
> - register 6 bit 6: eth_tx_en (DIF_3_P)
> - register 6 bit 8: eth_ref_clk (DIF_3_N)
> - register 6 bit 9: eth_mdc (DIF_4_P)
> - register 6 bit 10: eth_mdio_en (DIF_4_N)
> - register 6 bit 11: eth_tx_clk (GPIOH_9)
> - register 6 bit 12: eth_txd2 (GPIOH_8)
> - register 6 bit 13: eth_txd3 (GPIOH_7)
> - register 7 bit 20: eth_txd0_0 (GPIOH_6)
> - register 7 bit 21: eth_txd1_0 (GPIOH_5)
> - register 7 bit 22: eth_rxd3 (DIF_2_P)
> - register 7 bit 23: eth_rxd2 (DIF_2_N)
>
> Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the
> Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and
> eth_rxd3 groups so we don't rely on the bootloader to set them up.
>
> iperf3 statistics before this change:
> - transmitting from Odroid-C1: 741 Mbits/sec (0 retries)
> - receiving on Odroid-C1: 199 Mbits/sec (1713 retries)
>
> iperf3 statistics after this change:
> - transmitting from Odroid-C1: 667 Mbits/sec (0 retries)
> - receiving on Odroid-C1: 750 Mbits/sec (0 retries)
>
> Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Cc: Emiliano Ingrassia <ingrassia@epigenesys.com>
> Cc: Linus Lüssing <linus.luessing@c0d3.blue>
Queued for v5.1 (branch: v5.1/dt)
Kevin
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next prev parent reply other threads:[~2019-01-11 1:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-29 14:35 [PATCH v3 0/2] Meson8b RGMII Ethernet pin fixes Martin Blumenstingl
2018-12-29 14:35 ` [PATCH v3 1/2] pinctrl: meson: meson8b: add the eth_rxd2 and eth_rxd3 pins Martin Blumenstingl
2019-01-11 1:08 ` Kevin Hilman
2019-01-11 10:09 ` Emiliano Ingrassia
2019-01-11 18:06 ` Kevin Hilman
2019-01-11 18:21 ` Emiliano Ingrassia
2019-01-11 19:52 ` Martin Blumenstingl
2019-01-11 22:42 ` Kevin Hilman
2018-12-29 14:35 ` [PATCH v3 2/2] ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins Martin Blumenstingl
2019-01-11 1:09 ` Kevin Hilman [this message]
2019-01-11 10:13 ` Emiliano Ingrassia
2019-02-04 14:26 ` Martin Blumenstingl
2019-02-07 3:04 ` Kevin Hilman
2019-02-08 19:38 ` Martin Blumenstingl
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