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[71.197.186.152]) by smtp.googlemail.com with ESMTPSA id r12sm18045914pgv.83.2018.12.04.16.51.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 16:51:34 -0800 (PST) From: Kevin Hilman To: Martin Blumenstingl , carlo@caione.org, linux-amlogic@lists.infradead.org Subject: Re: [PATCH 0/6] 32-bit Meson: add the ARM TWD and Global Timers In-Reply-To: <20181123195311.4578-1-martin.blumenstingl@googlemail.com> References: <20181123195311.4578-1-martin.blumenstingl@googlemail.com> Date: Tue, 04 Dec 2018 16:51:33 -0800 Message-ID: <7hwooobxt6.fsf@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181204_165149_898968_18FC54AA X-CRM114-Status: GOOD ( 16.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Martin Blumenstingl writes: > The 32-bit Meson SoCs use Cortex-A9 or Cortex-A5 cores. These come > with the ARM TWD ("Timer Watchdog") which contains a timer and a > watchdog as well as the ARM Global Timer. > > This enables the corresponding configs for the 32-bit Meson target. > Additionally this adds and enables the ARM TWD timer. The Global > Timer is added but currently disabled because it's clock input is > the PERIPH clock which is derived from the CPU clock. Thus the rate > of the PERIPH clock will change when changing the CPU frequency. > Unfortunately the Global Timer driver doesn't handle clocks with > changing rates yet (unlike the TWD timer), thus we keep it disabled > for now. > > The whole series is inspired by an almost 3 year old patch from > Carlo: [0] > > > Dependencies: > - I build this on top of my other series "ARM: dts: meson: add the > timer interrupts and clocks" from [1] > - CLKID_PERIPH requires updated clock driver headers. Neil provided > a tag which includes the updated headers: [2] I pulled this branch into v4.21/dt > - There is no runtime dependency on the PERIPH clock as we don't > have CPU frequency scaling support enabled yet. In case the TWD > timer driver can't find the clock it falls back to auto-detecting > the clock rate at boot time. This is safe as long as we don't have > .dts patches in place which allow changing the CPU clock rate. Once > we enable CPU frequency scaling support for the PERIPH clock becomes > mandatory so the TWD timer driver knows about changes to the PERIPH > clock (which is derived from the CPU clock). > > > [0] https://patchwork.kernel.org/patch/7797581/ > [1] https://patchwork.kernel.org/cover/10687005/ > [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-November/009136.html > > > Martin Blumenstingl (6): > ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL_TIMER Applied to v4.21/defconfig > ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals > ARM: dts: meson8: add the ARM TWD timer > ARM: dts: meson8: add the Cortex-A9 global timer > ARM: dts: meson8b: add the ARM TWD timer > ARM: dts: meson8b: add the Cortex-A5 global timer Applied to v4.21/dt Kevin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel