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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l0403-0007Nb-MF; Thu, 14 Jan 2021 14:53:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l0401-0007NA-IK for linux-arm-kernel@lists.infradead.org; Thu, 14 Jan 2021 14:53:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38C49ED1; Thu, 14 Jan 2021 06:53:20 -0800 (PST) Received: from [10.37.12.3] (unknown [10.37.12.3]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 40A493F70D; Thu, 14 Jan 2021 06:53:18 -0800 (PST) Subject: Re: [PATCH v2 3/4] arm64: mte: Enable async tag check fault To: Catalin Marinas References: <20210107172908.42686-1-vincenzo.frascino@arm.com> <20210107172908.42686-4-vincenzo.frascino@arm.com> <20210113181121.GF27045@gaia> <20210114142512.GB16561@gaia> From: Vincenzo Frascino Message-ID: <80492795-4ebf-0d77-3f07-37593845a733@arm.com> Date: Thu, 14 Jan 2021 14:57:03 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210114142512.GB16561@gaia> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210114_095321_677696_318E2BEC X-CRM114-Status: GOOD ( 17.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Branislav Rankov , Marco Elver , Andrey Konovalov , Evgenii Stepanov , linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Alexander Potapenko , linux-arm-kernel@lists.infradead.org, Andrey Ryabinin , Will Deacon , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/14/21 2:25 PM, Catalin Marinas wrote: > On Thu, Jan 14, 2021 at 10:24:25AM +0000, Vincenzo Frascino wrote: >> On 1/13/21 6:11 PM, Catalin Marinas wrote: >>> On Thu, Jan 07, 2021 at 05:29:07PM +0000, Vincenzo Frascino wrote: >>>> static inline void mte_sync_tags(pte_t *ptep, pte_t pte) >>>> { >>>> } >>>> diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c >>>> index 5346953e4382..74b020ce72d7 100644 >>>> --- a/arch/arm64/kernel/entry-common.c >>>> +++ b/arch/arm64/kernel/entry-common.c >>>> @@ -37,6 +37,8 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs) >>>> lockdep_hardirqs_off(CALLER_ADDR0); >>>> rcu_irq_enter_check_tick(); >>>> trace_hardirqs_off_finish(); >>>> + >>>> + mte_check_tfsr_el1(); >>>> } >>>> >>>> /* >>>> @@ -47,6 +49,8 @@ static void noinstr exit_to_kernel_mode(struct pt_regs *regs) >>>> { >>>> lockdep_assert_irqs_disabled(); >>>> >>>> + mte_check_tfsr_el1(); >>>> + >>>> if (interrupts_enabled(regs)) { >>>> if (regs->exit_rcu) { >>>> trace_hardirqs_on_prepare(); >>>> @@ -243,6 +247,8 @@ asmlinkage void noinstr enter_from_user_mode(void) >>>> >>>> asmlinkage void noinstr exit_to_user_mode(void) >>>> { >>>> + mte_check_tfsr_el1(); >>> >>> While for kernel entry the asynchronous faults are sync'ed automatically >>> with TFSR_EL1, we don't have this for exit, so we'd need an explicit >>> DSB. But rather than placing it here, it's better if we add a bool sync >>> argument to mte_check_tfsr_el1() which issues a dsb() before checking >>> the register. I think that's the only place where such argument would be >>> true (for now). >> >> Good point, I will add the dsb() in mte_check_tfsr_el1() but instead of a bool >> parameter I will add something more explicit. > > Or rename the function to mte_check_tfsr_el1_no_sync() and have a static > inline mte_check_tfsr_el1() which issues a dsb() before calling the > *no_sync variant. > > Adding an enum instead here is not worth it (if that's what you meant by > not using a bool). > I like this option more, thanks for pointing it out. -- Regards, Vincenzo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel