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Fri, 11 Apr 2025 02:51:32 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53B2pU2w001014 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Apr 2025 02:51:30 GMT Received: from [10.239.133.242] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Apr 2025 19:51:27 -0700 Message-ID: <808b2ae5-5286-487c-8f52-03936c3686ef@quicinc.com> Date: Fri, 11 Apr 2025 10:51:24 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/7] coresight-tgu: add reset node to initialize To: Mike Leach CC: Suzuki K Poulose , James Clark , Alexander Shishkin , Andy Gross , "Bjorn Andersson" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , , , , , Songwei Chai References: <20250227092640.2666894-1-quic_songchai@quicinc.com> <20250227092640.2666894-8-quic_songchai@quicinc.com> Content-Language: en-US From: songchai In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=VbH3PEp9 c=1 sm=1 tr=0 ts=67f883b4 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=vmeuUHBbrc6izfGtevMA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: M3FgirXRwWiVEtVfkR1R1N9M31nazOhl X-Proofpoint-ORIG-GUID: M3FgirXRwWiVEtVfkR1R1N9M31nazOhl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 bulkscore=0 mlxscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110020 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_195142_578486_4BC07054 X-CRM114-Status: GOOD ( 22.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 3/7/2025 9:33 PM, Mike Leach wrote: > Hi, > > On Thu, 27 Feb 2025 at 09:27, songchai wrote: >> From: Songwei Chai >> >> Add reset node to initialize the value of >> priority/condition_decode/condition_select/timer/counter nodes >> >> Signed-off-by: Songwei Chai >> Signed-off-by: songchai >> --- >> .../testing/sysfs-bus-coresight-devices-tgu | 7 ++ >> drivers/hwtracing/coresight/coresight-tgu.c | 79 +++++++++++++++++++ >> 2 files changed, 86 insertions(+) >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu >> index d88d05fbff43..8fb5afd7c655 100644 >> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu >> @@ -42,3 +42,10 @@ KernelVersion 6.15 >> Contact: Jinlong Mao (QUIC) , Sam Chai (QUIC) >> Description: >> (RW) Set/Get the counter value with specific step for TGU. >> + >> +What: /sys/bus/coresight/devices//reset_tgu >> +Date: February 2025 >> +KernelVersion 6.15 >> +Contact: Jinlong Mao (QUIC) , Sam Chai (QUIC) >> +Description: >> + (Write) Reset the dataset for TGU. > Document the value needed to initiate the reset. Done. > >> diff --git a/drivers/hwtracing/coresight/coresight-tgu.c b/drivers/hwtracing/coresight/coresight-tgu.c >> index 693d632fb079..b36ced761c0d 100644 >> --- a/drivers/hwtracing/coresight/coresight-tgu.c >> +++ b/drivers/hwtracing/coresight/coresight-tgu.c >> @@ -343,6 +343,84 @@ static ssize_t enable_tgu_store(struct device *dev, >> } >> static DEVICE_ATTR_RW(enable_tgu); >> >> +/* reset_tgu_store - Reset Trace and Gating Unit (TGU) configuration. */ >> +static ssize_t reset_tgu_store(struct device *dev, >> + struct device_attribute *attr, const char *buf, >> + size_t size) >> +{ >> + unsigned long value; >> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + int i, j, ret; >> + >> + if (kstrtoul(buf, 0, &value)) >> + return -EINVAL; >> + > Check "value" here and bail out with an error code if 0. Done. > >> + if (!drvdata->enable) { >> + ret = pm_runtime_get_sync(drvdata->dev); >> + if (ret < 0) { >> + pm_runtime_put(drvdata->dev); >> + return ret; >> + } >> + } >> + >> + spin_lock(&drvdata->spinlock); >> + CS_UNLOCK(drvdata->base); >> + >> + if (value) { > drop this line Done. > >> + tgu_writel(drvdata, 0, TGU_CONTROL); >> + >> + if (drvdata->value_table->priority) >> + memset(drvdata->value_table->priority, 0, >> + MAX_PRIORITY * drvdata->max_step * >> + drvdata->max_reg * sizeof(unsigned int)); >> + >> + if (drvdata->value_table->condition_decode) >> + memset(drvdata->value_table->condition_decode, 0, >> + drvdata->max_condition_decode * drvdata->max_step * >> + sizeof(unsigned int)); >> + >> + /* Initialize all condition registers to NOT(value=0x1000000) */ >> + for (i = 0; i < drvdata->max_step; i++) { >> + for (j = 0; j < drvdata->max_condition_decode; j++) { >> + drvdata->value_table >> + ->condition_decode[calculate_array_location( >> + drvdata, i, TGU_CONDITION_DECODE, j)] = >> + 0x1000000; >> + } >> + } >> + >> + if (drvdata->value_table->condition_select) >> + memset(drvdata->value_table->condition_select, 0, >> + drvdata->max_condition_select * drvdata->max_step * >> + sizeof(unsigned int)); >> + >> + if (drvdata->value_table->timer) >> + memset(drvdata->value_table->timer, 0, >> + (drvdata->max_step) * >> + (drvdata->max_timer_counter) * >> + sizeof(unsigned int)); >> + >> + if (drvdata->value_table->counter) >> + memset(drvdata->value_table->counter, 0, >> + (drvdata->max_step) * >> + (drvdata->max_timer_counter) * >> + sizeof(unsigned int)); >> + >> + dev_dbg(dev, "Coresight-TGU reset complete\n"); >> + } else { >> + dev_dbg(dev, "Coresight-TGU invalid input\n"); > not needed if early exit on input errror Done. > >> + } >> + >> + CS_LOCK(drvdata->base); >> + >> + drvdata->enable = false; >> + spin_unlock(&drvdata->spinlock); >> + pm_runtime_put(drvdata->dev); >> + >> + return size; >> +} >> +static DEVICE_ATTR_WO(reset_tgu); >> + >> static const struct coresight_ops_helper tgu_helper_ops = { >> .enable = tgu_enable, >> .disable = tgu_disable, >> @@ -354,6 +432,7 @@ static const struct coresight_ops tgu_ops = { >> >> static struct attribute *tgu_common_attrs[] = { >> &dev_attr_enable_tgu.attr, >> + &dev_attr_reset_tgu.attr, >> NULL, >> }; >> >> > > Regards > > Mike >