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Thu, 8 May 2025 20:03:45 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 21/23] iommu/tegra241-cmdqv: Do not statically map LVCMDQs Date: Thu, 8 May 2025 20:02:42 -0700 Message-ID: <80d41b740635b40dd0f9ed4279dc1cdeb3c8942c.1746757630.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|SA0PR12MB7461:EE_ X-MS-Office365-Filtering-Correlation-Id: c5998a92-2205-4dc4-d8a5-08dd8ea623de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?202ETSjcH2gfVCUgOCPEZfdKZ/EvhJYTh/42eNuyyI3bc5lFZsI/nM5g/o/+?= =?us-ascii?Q?8EgX2UVUntgFGVK/CYfKyvGE2Z3/f//WULqe0UdZdn2fVV20KzLomKEuCYIG?= =?us-ascii?Q?4mWzOFEBtjIVhxRm07Ads9lG7jtiZXjyTjSnEnTlgcDRLlsEAD7xSMNwWuTN?= =?us-ascii?Q?ifEWq3Y+VO5jEwlvHxQ07QIlgcmTvxhpk6BTUIjFUp2lsYCEbz9TXwQsFDOX?= =?us-ascii?Q?HFOw1DPADvN8OFq/Dskhn0p7vGz3RjzZ2wTEUvkCdSyaRz1JzvGlKn/I9YaZ?= =?us-ascii?Q?GBlra2RkEW7WCnvA85j9XuFl+FQtJEVwyUzaOoIhrM9rXyoZnmByw61X/lc4?= =?us-ascii?Q?yo/YktNowLlKqYhjHleXALzKgYNtyOuINlnbbAKgVHhNIZTNQPoi0eKN6T99?= =?us-ascii?Q?ZoXsxDRy2ljwkhse1nrNRnJlsgh689biCQ7tcly5V6/GdkVb99jZ5cQLQUKR?= =?us-ascii?Q?PbyAJZGNKzdl3Xpwiksvya483PwlPLTooVWlt2jHE7RzQ1tK/TFwsUWMs/Do?= =?us-ascii?Q?5H3jAWu++1xdBmy1tfAf/OOnE++h3GCEDLo6DXpK/+WuWrcNO31y8hVMeBst?= =?us-ascii?Q?q0qT2OZ0hveXrGI32q6LCUJD6ar30CnavzOLHcp4/5qCgpqMGrU96UvkDRv0?= =?us-ascii?Q?r0GpluKjJrrzk032+bcFO9h+gtJq0aI6KbRXq/zZF6mG114s7HEoBhZ2ZntR?= =?us-ascii?Q?gnq+lyNXQxaYE9C41uVy0GhDbIKu6QnzATLlCJxRGJX+BsiQSemR4YFmuZIS?= =?us-ascii?Q?glPYVGaAS2t+d/GA/5tWMXnx7ULMEDP9gOTrR/Fj6bIGw0zoM6/aPBEqVmPG?= =?us-ascii?Q?BtlyuUQmqUH3lmQaOvoQHLmpdPgrKpxhzMSd9ZynKU2jQMYSv0mxiPEJI17a?= =?us-ascii?Q?/gfVCBAvqZQqM2MJ70K146V2k/Qux5SwzBn4cIUm9skl39OZhQiiEtlLW32K?= =?us-ascii?Q?AstxFged5mSadYBo/SnqbNmW7bHdMofls52lnEkLmA/SJhABjoRh9rihO3S7?= =?us-ascii?Q?P+nMmj94StgghWgT9ReBUI5q0nLW/lu4du3UHaGsC0yfzrdsvYWtZd2g2wYd?= =?us-ascii?Q?X36UilcL6dHn6XOv2GqXof8ZY5j5nM70+awyET5sbXJAI2dj2pyoR3GEqzQs?= =?us-ascii?Q?U2Khmxc2M4dwQehXqKkinPuU5eQ5/rHzQhIKSUCM6WCoc2EtyCt7scG/N2kc?= =?us-ascii?Q?OEZ/nhoxtw4KMqBGzdmRYkkjgPZd3atrNuCr6TyEZbbah/QFHuetsfc3+H3S?= =?us-ascii?Q?DTODDKIUNX476K6GY5O6oYKYwqx7ktWbZZMNgOOIeWlVcVz+eR9wwxdED273?= =?us-ascii?Q?K++dOaixAGTbqxnUl6bwltyqQxUiYzRjuBBUpbnqZbAfTvz37gygtXicnJzA?= =?us-ascii?Q?fVC/EODmWOuE9ZXWI8QziO0Uy7ar63Y3BlEJN+sl/oZJASDdf/e2USS5CNjp?= =?us-ascii?Q?I1dHGIkZ6e+iqy/T1l/RW7ex/l3sl674mOpN1ocvI0p8VkX9KgMtcnfw3agW?= =?us-ascii?Q?oy/Kw1akW2zIP+DxpwIJfTq3rqOl8goeezMs?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2025 03:03:57.2682 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5998a92-2205-4dc4-d8a5-08dd8ea623de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7461 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250508_200404_652457_9DCDA696 X-CRM114-Status: GOOD ( 15.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To simplify the mappings from global VCMDQs to VINTFs' LVCMDQs, the design chose to do static allocations and mappings in the global reset function. However, with the user-owned VINTF support, it exposes a security concern: if user space VM only wants one LVCMDQ for a VINTF, statically mapping two or more LVCMDQs creates a hidden VCMDQ that user space could DoS attack by writing random stuff to overwhelm the kernel with unhandleable IRQs. Thus, to support the user-owned VINTF feature, a LVCMDQ mapping has to be done dynamically. HW allows pre-assigning global VCMDQs in the CMDQ_ALLOC registers, without finalizing the mappings by keeping CMDQV_CMDQ_ALLOCATED=0. So, add a pair of map/unmap helper that simply sets/clears that bit. Delay the LVCMDQ mappings to tegra241_vintf_hw_init(), and the unmappings to tegra241_vintf_hw_deinit(). However, the dynamic LVCMDQ mapping/unmapping can complicate the timing of calling tegra241_vcmdq_hw_init/deinit(), which write LVCMDQ address space, i.e. requiring LVCMDQ to be mapped. Highlight that with a note to the top of either of them. Acked-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 37 +++++++++++++++++-- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 8d418c131b1b..869c90b660c1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -351,6 +351,7 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, /* HW Reset Functions */ +/* This function is for LVCMDQ, so @vcmdq must not be unmapped yet */ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -379,6 +380,7 @@ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h); } +/* This function is for LVCMDQ, so @vcmdq must be mapped prior */ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -404,16 +406,42 @@ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) return 0; } +/* Unmap a global VCMDQ from the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_unmap_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval & ~CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%sunmapped\n", h); +} + static void tegra241_vintf_hw_deinit(struct tegra241_vintf *vintf) { - u16 lidx; + u16 lidx = vintf->cmdqv->num_lvcmdqs_per_vintf; - for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) - if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) + /* HW requires to unmap LVCMDQs in descending order */ + while (lidx--) { + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + tegra241_vcmdq_unmap_lvcmdq(vintf->lvcmdqs[lidx]); + } + } vintf_write_config(vintf, 0); } +/* Map a global VCMDQ to the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_map_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval | CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%smapped\n", h); +} + static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) { u32 regval; @@ -441,8 +469,10 @@ static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) */ vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG))); + /* HW requires to map LVCMDQs in ascending order */ for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { + tegra241_vcmdq_map_lvcmdq(vintf->lvcmdqs[lidx]); ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]); if (ret) { tegra241_vintf_hw_deinit(vintf); @@ -476,7 +506,6 @@ static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu) for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); - regval |= CMDQV_CMDQ_ALLOCATED; writel_relaxed(regval, REG_CMDQV(cmdqv, CMDQ_ALLOC(qidx++))); } -- 2.43.0