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Tue, 21 Jul 2026 07:59:05 -0700 (PDT) Received: from [192.168.136.254] ([94.232.27.38]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69e6fee248asm6113634a12.1.2026.07.21.07.59.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 07:59:04 -0700 (PDT) Message-ID: <816442c5-88fe-49b6-92a3-cf924c056ae8@gmail.com> Date: Tue, 21 Jul 2026 19:48:04 +0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] pinctrl: rockchip: add support for RK3308B SoC To: Hugo VALTIER Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Luca Ceresoli , Jonas Karlman , Linus Walleij , Heiko Stuebner , Dmitry Yashin References: <20260717075918.1869879-1-hugo@ahdrone.com> <20260717075918.1869879-4-hugo@ahdrone.com> From: Dmitry Yashin Content-Language: en-US In-Reply-To: <20260717075918.1869879-4-hugo@ahdrone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260721_075907_658999_45E288BF X-CRM114-Status: GOOD ( 22.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/17/26 12:59, Hugo VALTIER wrote: > The RK3308B is a revision of the RK3308 including different iomux > register layout. > Several pins (GPIO2_A2, GPIO2_A3, GPIO2_C0, GPIO3_B2, GPIO3_B3) > have 3-bit mux fields in new GRF registers (SOC_CON13 at 0x608 and > SOC_CON15 at 0x610) that override the standard 2-bit fields. > I believe the bootloader sets the sel_src_ctrl bits to activate these > new registers, which causes the kernel's writes to the old 2-bit iomux > registers to be silently ignored. > > Without this patch, SPI1, I2C3, and other peripherals that depend on > these pins are completely non-functional on my RK3308B boards. > > Detect the SoC variant at runtime by reading the chip_id register at GRF > offset 0x800 (0xcea = RK3308, 0x3308/0x3308c = RK3308B), as requested > by reviewers of the earlier series. > When RK3308B is detected, swap in the correct mux_recalced and mux_route > tables and write the sel_src_ctrl bits to ensure the 3-bit mux registers > are active. > > This is a rework of Dmitry Yashin's series [1] which used a separate > device tree compatible string ("rockchip,rk3308b-pinctrl") to > distinguish the variants. > Reviewers Luca Ceresoli and Heiko Stuebner agreed that runtime detection > was preferable since boards are manufactured with both RK3308 and RK3308B > using the same device tree. > > Jonas Karlman implemented runtime detection based on the GRF_CHIP_ID > register [2]. Reviewers asked for more changes (constifying some > arrays), but the series was never resubmitted and was dropped. > > I run this patch on my Rock Pi S boards, the newer ones I've got in > 2024 use the RK3308B. And thanks to runtime detection we should still > be compatible with older devices (but I couldn't test on RK3308 as I > don't have any). > > [1] https://lore.kernel.org/all/20240515121634.23945-1-dmt.yashin@gmail.com/ > [2] https://lore.kernel.org/all/20240604141020.21725-1-dmt.yashin@gmail.com/ > > Signed-off-by: Hugo VALTIER > --- Hi Hugo. Thanks for re-sending the series! Applied patches to multiple boards and it fixes pinmux issues for rk3308b-s based boards too (since the approach kept the same as in v3 series) Tested-by: Dmitry Yashin -- Dmt-Y