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([2a01:e0a:982:cbb0:2f85:a28c:5df7:9cd2]) by smtp.gmail.com with ESMTPSA id j5-20020a5d5645000000b00225307f43fbsm13038696wrw.44.2022.11.29.00.41.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Nov 2022 00:41:10 -0800 (PST) Message-ID: <81e5bd05-b081-8072-b09d-30e32834163e@linaro.org> Date: Tue, 29 Nov 2022 09:41:11 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 From: Neil Armstrong Subject: Re: [PATCH v2 2/2] drm/tiny: ili9486: Do not assume 8-bit only SPI controllers Content-Language: en-US To: Carlo Caione , Mark Brown , Daniel Vetter , David Airlie , Martin Blumenstingl , Kevin Hilman , Kamlesh Gurudasani , Jerome Brunet Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20221116-s905x_spi_ili9486-v2-0-084c6e3cd930@baylibre.com> <20221116-s905x_spi_ili9486-v2-2-084c6e3cd930@baylibre.com> Organization: Linaro Developer Services In-Reply-To: <20221116-s905x_spi_ili9486-v2-2-084c6e3cd930@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_004113_320482_5D8873CA X-CRM114-Status: GOOD ( 31.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: neil.armstrong@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 21/11/2022 10:42, Carlo Caione wrote: > The pixel data for the ILI9486 is always 16-bits wide and it must be > sent over the SPI bus. When the controller is only able to deal with > 8-bit transfers, this 16-bits data needs to be swapped before the > sending to account for the big endian bus, this is on the contrary not > needed when the SPI controller already supports 16-bits transfers. > > The decision about swapping the pixel data or not is taken in the MIPI > DBI code by probing the controller capabilities: if the controller only > suppors 8-bit transfers the data is swapped, otherwise it is not. > > This swapping/non-swapping is relying on the assumption that when the > controller does support 16-bit transactions then the data is sent > unswapped in 16-bits-per-word over SPI. > > The problem with the ILI9486 driver is that it is forcing 8-bit > transactions also for controllers supporting 16-bits, violating the > assumption and corrupting the pixel data. > > Align the driver to what is done in the MIPI DBI code by adjusting the > tranfer size to the maximum allowed by the SPI controller. > > Signed-off-by: Carlo Caione > --- > drivers/gpu/drm/tiny/ili9486.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/tiny/ili9486.c b/drivers/gpu/drm/tiny/ili9486.c > index bd37dfe8dd05..4d80a413338f 100644 > --- a/drivers/gpu/drm/tiny/ili9486.c > +++ b/drivers/gpu/drm/tiny/ili9486.c > @@ -43,6 +43,7 @@ static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par, > size_t num) > { > struct spi_device *spi = mipi->spi; > + unsigned int bpw = 8; > void *data = par; > u32 speed_hz; > int i, ret; > @@ -56,8 +57,6 @@ static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par, > * The displays are Raspberry Pi HATs and connected to the 8-bit only > * SPI controller, so 16-bit command and parameters need byte swapping > * before being transferred as 8-bit on the big endian SPI bus. > - * Pixel data bytes have already been swapped before this function is > - * called. > */ > buf[0] = cpu_to_be16(*cmd); > gpiod_set_value_cansleep(mipi->dc, 0); > @@ -71,12 +70,18 @@ static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par, > for (i = 0; i < num; i++) > buf[i] = cpu_to_be16(par[i]); > num *= 2; > - speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); > data = buf; > } > > + /* > + * Check whether pixel data bytes needs to be swapped or not > + */ > + if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !mipi->swap_bytes) > + bpw = 16; > + > gpiod_set_value_cansleep(mipi->dc, 1); > - ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, data, num); > + speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); > + ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, data, num); > free: > kfree(buf); > > Looks fine, but should somehow be tested on an RPi first to check if the 8bit fallback still works. Reviewed-by: Neil Armstrong _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel