From: Marc Zyngier <maz@kernel.org>
To: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Marek Vasut <marex@denx.de>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Patrick Delaunay <patrick.delaunay@st.com>,
linux-stm32@st-md-mailman.stormreply.com,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: STM32MP1 level triggered interrupts
Date: Tue, 21 Jan 2020 17:21:38 +0000 [thread overview]
Message-ID: <82d4619107e9ac76d317268637f050cf@kernel.org> (raw)
In-Reply-To: <d6e02817-2464-51b9-246a-7720b607b8d6@st.com>
On 2020-01-21 17:12, Alexandre Torgue wrote:
> Hi Marek,
>
> On 1/20/20 7:32 PM, Marek Vasut wrote:
>> Hi,
>>
>> I have a device connected to STM32MP157C which requires active-low
>> level-triggered interrupt sink. The device interrupt line is connected
>> to the SoC gpio-C bank, which has it's interrupt line routed into
>> EXTI,
>> which can only handle edge triggered interrupts to my understanding.
>
> correct.
>
>>
>> However, ARM GIC should be able to do both and EXTI has this irqmux /
>> EXTImux functionality, which -- if my understanding is correct -- is
>> capable of routing a select GPIO line directly into the GIC as an
>> EXTIn
>> interrupt signal. Thus, this might permit handling active low
>> level-triggered interrupts. Is there some DT binding to configure this
>> yet ?
>>
>> Or is there some other, better, way ?
>>
>
> For SPIs, GIC controller handles rising edge triggered interrupt and
> active high level-sensitive. GIC integration in STM32MP157c makes that
> only active high level-sensitive configuration for SPI interrupts is
> supported.
This statement is a slight exaggeration. *any* GIC will happily service
rising-edge triggered SPIs, as it is mandated by the spec. What I
suspect
is that there is no SPI that is routed out of the SoC for anyone to
directly
plug anything into it.
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2020-01-21 17:21 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-20 18:32 STM32MP1 level triggered interrupts Marek Vasut
2020-01-21 17:12 ` Alexandre Torgue
2020-01-21 17:21 ` Marc Zyngier [this message]
2020-01-22 16:56 ` Alexandre Torgue
2020-01-21 17:41 ` Marek Vasut
2020-01-22 17:19 ` Alexandre Torgue
2020-01-22 19:29 ` Marek Vasut
2020-01-23 8:27 ` Alexandre Torgue
2020-01-23 9:22 ` Marc Zyngier
2020-01-23 10:12 ` Uwe Kleine-König
2020-01-23 10:44 ` Marc Zyngier
2020-01-23 10:52 ` Uwe Kleine-König
2020-01-23 11:18 ` Marc Zyngier
2020-01-23 22:21 ` Marek Vasut
2020-01-24 9:17 ` Alexandre Torgue
2020-01-24 9:24 ` Marc Zyngier
2020-01-28 18:32 ` Marek Vasut
2020-02-05 10:26 ` Marek Vasut
2020-02-05 11:42 ` Marc Zyngier
2020-02-05 11:53 ` Marek Vasut
2020-02-05 12:32 ` Marc Zyngier
2020-02-05 15:36 ` Alexandre TORGUE
2020-02-06 2:00 ` Marek Vasut
2020-01-24 12:25 ` Marek Vasut
2020-01-24 9:21 ` Marc Zyngier
2020-01-24 9:35 ` Alexandre Torgue
2020-01-23 22:21 ` Marek Vasut
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