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Tue, 21 Jan 2020 17:21:38 +0000 MIME-Version: 1.0 Date: Tue, 21 Jan 2020 17:21:38 +0000 From: Marc Zyngier To: Alexandre Torgue Subject: Re: STM32MP1 level triggered interrupts In-Reply-To: References: <20bb72d0-8258-abc0-e729-4d3d5a75c41c@denx.de> Message-ID: <82d4619107e9ac76d317268637f050cf@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.8 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: alexandre.torgue@st.com, marex@denx.de, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, mcoquelin.stm32@gmail.com, patrick.delaunay@st.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200121_092140_576735_E406A9BF X-CRM114-Status: GOOD ( 10.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Maxime Coquelin , Patrick Delaunay , linux-stm32@st-md-mailman.stormreply.com, Linux ARM Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-01-21 17:12, Alexandre Torgue wrote: > Hi Marek, > > On 1/20/20 7:32 PM, Marek Vasut wrote: >> Hi, >> >> I have a device connected to STM32MP157C which requires active-low >> level-triggered interrupt sink. The device interrupt line is connected >> to the SoC gpio-C bank, which has it's interrupt line routed into >> EXTI, >> which can only handle edge triggered interrupts to my understanding. > > correct. > >> >> However, ARM GIC should be able to do both and EXTI has this irqmux / >> EXTImux functionality, which -- if my understanding is correct -- is >> capable of routing a select GPIO line directly into the GIC as an >> EXTIn >> interrupt signal. Thus, this might permit handling active low >> level-triggered interrupts. Is there some DT binding to configure this >> yet ? >> >> Or is there some other, better, way ? >> > > For SPIs, GIC controller handles rising edge triggered interrupt and > active high level-sensitive. GIC integration in STM32MP157c makes that > only active high level-sensitive configuration for SPI interrupts is > supported. This statement is a slight exaggeration. *any* GIC will happily service rising-edge triggered SPIs, as it is mandated by the spec. What I suspect is that there is no SPI that is routed out of the SoC for anyone to directly plug anything into it. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel