From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 704D9C3A5A9 for ; Mon, 4 May 2020 14:37:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 212632078E for ; Mon, 4 May 2020 14:37:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sVlaJb+u" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 212632078E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Uzvgmy6QJ24xbSUjaB35G6oa5U1BME3NOy7HopT10tE=; b=sVlaJb+u4c698U5+RhraSZj3A Lld6AtpyrgVWfnjCdXTEJqnvwrl1ztcPFbd30Q8eRUYU6fKcrbSbq2WdVRgapHzalg31Dm2iG09Tl wAN8gBObMLpwWTYeMzjhnfOveot9lUw3DRnBLMeXeKjFbu651AcIpqyxBMg3SvFB3mvYHqRf4W1lF EHmr94blxoAz76Hlcau1Hju7s/7DNhXO8yrbA4d7mVJ8o3JUbo3bDlfS4HQrN3Yx7i30/mlM9Reu+ jQHSSHXelJslUhdu+AK59Fl29IvmJAyubqS9TgRa93at+47vTZnspNY+by3n6XUm2uao2Ji1Kgb3h 6He/CWLMA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jVcDi-0003TO-6n; Mon, 04 May 2020 14:37:22 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jVcDe-0003SE-BQ for linux-arm-kernel@lists.infradead.org; Mon, 04 May 2020 14:37:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D6461FB; Mon, 4 May 2020 07:37:17 -0700 (PDT) Received: from [10.37.12.17] (unknown [10.37.12.17]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 543783F305; Mon, 4 May 2020 07:37:04 -0700 (PDT) Subject: Re: [PATCH v6 11/25] iommu/arm-smmu-v3: Share process page tables To: jean-philippe@linaro.org References: <20200430143424.2787566-1-jean-philippe@linaro.org> <20200430143424.2787566-12-jean-philippe@linaro.org> <580a915f-f8bf-3b3e-c77d-6d0c2ea4bd02@arm.com> <20200504141137.GA170104@myrica> From: Suzuki K Poulose Message-ID: <82f54362-34f1-2378-49c2-2d87e065e385@arm.com> Date: Mon, 4 May 2020 15:42:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200504141137.GA170104@myrica> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200504_073718_438763_DCD1B046 X-CRM114-Status: GOOD ( 16.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, kevin.tian@intel.com, jacob.jun.pan@linux.intel.com, jgg@ziepe.ca, linux-pci@vger.kernel.org, joro@8bytes.org, Jonathan.Cameron@huawei.com, robin.murphy@arm.com, fenghua.yu@intel.com, hch@infradead.org, linux-mm@kvack.org, iommu@lists.linux-foundation.org, zhangfei.gao@linaro.org, catalin.marinas@arm.com, felix.kuehling@amd.com, xuzaibo@huawei.com, will@kernel.org, christian.koenig@amd.com, linux-arm-kernel@lists.infradead.org, baolu.lu@linux.intel.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 05/04/2020 03:11 PM, Jean-Philippe Brucker wrote: > On Thu, Apr 30, 2020 at 04:39:53PM +0100, Suzuki K Poulose wrote: >> On 04/30/2020 03:34 PM, Jean-Philippe Brucker wrote: >>> With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR, >>> MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split >>> into two sets, shared and private. Shared ASIDs correspond to those >>> obtained from the arch ASID allocator, and private ASIDs are used for >>> "classic" map/unmap DMA. >>> >>> Cc: Suzuki K Poulose >>> Signed-off-by: Jean-Philippe Brucker >>> --- >> >>> + >>> + tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - VA_BITS) | >>> + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) | >>> + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) | >>> + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) | >>> + CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; >>> + >>> + switch (PAGE_SIZE) { >>> + case SZ_4K: >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K); >>> + break; >>> + case SZ_16K: >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K); >>> + break; >>> + case SZ_64K: >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K); >>> + break; >>> + default: >>> + WARN_ON(1); >>> + ret = -EINVAL; >>> + goto err_free_asid; >>> + } >>> + >>> + reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); >>> + par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT); >>> + tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par); >>> + >>> + cd->ttbr = virt_to_phys(mm->pgd); >> >> Does the TTBR follow the same layout as TTBR_ELx for 52bit IPA ? i.e, >> TTBR[5:2] = BADDR[51:48] ? Are you covered for that ? > > Good point, I don't remember checking this. The SMMU TTBR doesn't have the > same layout as the CPU's, and we don't need to swizzle the bits. For the > lower bits, the alignment requirements on the pgd are identical to the > MMU. Ok, if that is the case: Acked-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel