[PATCH 0/3] imx8qm/imx8qxp: Support for inverted PWM

[PATCH 0/3] imx8qm/imx8qxp: Support for inverted PWM

[Alexander Stein]

Hi,

this small series adds support for inverted PWM output i.MX8QM/QXP.
Driver is already there, but #pwm-cells needs to be adjusted in DT.
While at it, also DT bindings constraints are added to ensure the proper value.

Thanks
Alexander

Alexander Stein (3):
  dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells
  arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells
  arm64: dts: freescale: imx8-ss-dma: Fix #pwm-cells

 .../devicetree/bindings/pwm/imx-pwm.yaml      | 20 ++++++++++++++++---
 .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi |  2 +-
 .../boot/dts/freescale/imx8-ss-lsio.dtsi      |  8 ++++----
 3 files changed, 22 insertions(+), 8 deletions(-)

-- 
2.34.1


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[PATCH 1/3] dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells

[Alexander Stein]

Only fsl,imx1-pwm comptabile devices use #pwm-cells = <2>. Newer SoCs
supportinverted PWM output, thus #pwm-cells needs to be set to 3.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../devicetree/bindings/pwm/imx-pwm.yaml      | 20 ++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
index c01dff3b7f843..59a981c0f39ab 100644
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
@@ -9,9 +9,6 @@ title: Freescale i.MX PWM controller
 maintainers:
   - Philipp Zabel <p.zabel@pengutronix.de>
 
-allOf:
-  - $ref: pwm.yaml#
-
 properties:
   "#pwm-cells":
     description: |
@@ -74,6 +71,23 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - $ref: pwm.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx1-pwm
+    then:
+      properties:
+        "#pwm-cells":
+          enum: [2]
+    else:
+      properties:
+        "#pwm-cells":
+          enum: [3]
+
 examples:
   - |
     #include <dt-bindings/clock/imx5-clock.h>
-- 
2.34.1


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[PATCH 2/3] arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells

[Alexander Stein]

i.MX8QM/QXP supports inverted PWM output, thus #pwm-cells needs to be set
to 3.

Fixes: a05c329644d81 ("arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 49ad3413db948..7e510b21bbac5 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -29,7 +29,7 @@ lsio_pwm0: pwm@5d000000 {
 			 <&pwm0_lpcg 1>;
 		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
+		#pwm-cells = <3>;
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
@@ -42,7 +42,7 @@ lsio_pwm1: pwm@5d010000 {
 			 <&pwm1_lpcg 1>;
 		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
+		#pwm-cells = <3>;
 		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
@@ -55,7 +55,7 @@ lsio_pwm2: pwm@5d020000 {
 			 <&pwm2_lpcg 1>;
 		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
+		#pwm-cells = <3>;
 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
@@ -68,7 +68,7 @@ lsio_pwm3: pwm@5d030000 {
 			 <&pwm3_lpcg 1>;
 		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
+		#pwm-cells = <3>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
-- 
2.34.1


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[PATCH 3/3] arm64: dts: freescale: imx8-ss-dma: Fix #pwm-cells

[Alexander Stein]

i.MX8QXP supports inverted PWM output, thus #pwm-cells needs to be set
to 3.

Fixes: f1d6a6b991ef9 ("arm64: dts: imx8qxp: add adma_pwm in adma")
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index ce66d30a4839b..b0bb77150adcc 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -149,7 +149,7 @@ adma_pwm: pwm@5a190000 {
 		clock-names = "ipg", "per";
 		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <24000000>;
-		#pwm-cells = <2>;
+		#pwm-cells = <3>;
 		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
 	};
 
-- 
2.34.1


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Re: [PATCH 1/3] dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells

[Uwe Kleine-König]

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Hello,

[dropped Philippe Schenker from Cc as his email bounced in the past]

On Mon, Nov 06, 2023 at 10:52:03AM +0100, Alexander Stein wrote:
> Only fsl,imx1-pwm comptabile devices use #pwm-cells = <2>. Newer SoCs
> supportinverted PWM output, thus #pwm-cells needs to be set to 3.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  .../devicetree/bindings/pwm/imx-pwm.yaml      | 20 ++++++++++++++++---
>  1 file changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> index c01dff3b7f843..59a981c0f39ab 100644
> --- a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> @@ -9,9 +9,6 @@ title: Freescale i.MX PWM controller
>  maintainers:
>    - Philipp Zabel <p.zabel@pengutronix.de>
>  
> -allOf:
> -  - $ref: pwm.yaml#
> -
>  properties:
>    "#pwm-cells":
>      description: |
> @@ -74,6 +71,23 @@ required:
>  
>  additionalProperties: false
>  
> +allOf:
> +  - $ref: pwm.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: fsl,imx1-pwm
> +    then:
> +      properties:
> +        "#pwm-cells":
> +          enum: [2]

Given that arch/arm/boot/dts/nxp/imx/imx1.dtsi has:

	pwm: pwm@208000 {
		#pwm-cells = <3>;
		compatible = "fsl,imx1-pwm";
		...

this looks wrong.

Best regards
Uwe

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Re: [PATCH 2/3] arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells

[Uwe Kleine-König]

[-- Attachment #1.1: Type: text/plain, Size: 2406 bytes --]

Hello,

[again Cc -= Philippe Schenker]

On Mon, Nov 06, 2023 at 10:52:04AM +0100, Alexander Stein wrote:
> i.MX8QM/QXP supports inverted PWM output, thus #pwm-cells needs to be set
> to 3.
> 
> Fixes: a05c329644d81 ("arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3")
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> index 49ad3413db948..7e510b21bbac5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> @@ -29,7 +29,7 @@ lsio_pwm0: pwm@5d000000 {
>  			 <&pwm0_lpcg 1>;
>  		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
>  		assigned-clock-rates = <24000000>;
> -		#pwm-cells = <2>;
> +		#pwm-cells = <3>;
>  		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> @@ -42,7 +42,7 @@ lsio_pwm1: pwm@5d010000 {
>  			 <&pwm1_lpcg 1>;
>  		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
>  		assigned-clock-rates = <24000000>;
> -		#pwm-cells = <2>;
> +		#pwm-cells = <3>;
>  		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> @@ -55,7 +55,7 @@ lsio_pwm2: pwm@5d020000 {
>  			 <&pwm2_lpcg 1>;
>  		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
>  		assigned-clock-rates = <24000000>;
> -		#pwm-cells = <2>;
> +		#pwm-cells = <3>;
>  		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> @@ -68,7 +68,7 @@ lsio_pwm3: pwm@5d030000 {
>  			 <&pwm3_lpcg 1>;
>  		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
>  		assigned-clock-rates = <24000000>;
> -		#pwm-cells = <2>;
> +		#pwm-cells = <3>;
>  		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};

Even without patch #1 this is a good change. There are no usages of the
lsio_pwm* handles as of today's next. So no consumers need adaption.

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Best regards
Uwe

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Re: [PATCH 1/3] dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells

[Alexander Stein]

Hello Uwe,

Am Montag, 6. November 2023, 11:36:21 CET schrieb Uwe Kleine-König:
> Hello,
> 
> [dropped Philippe Schenker from Cc as his email bounced in the past]
> 
> On Mon, Nov 06, 2023 at 10:52:03AM +0100, Alexander Stein wrote:
> > Only fsl,imx1-pwm comptabile devices use #pwm-cells = <2>. Newer SoCs
> > supportinverted PWM output, thus #pwm-cells needs to be set to 3.
> > 
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> > 
> >  .../devicetree/bindings/pwm/imx-pwm.yaml      | 20 ++++++++++++++++---
> >  1 file changed, 17 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> > b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml index
> > c01dff3b7f843..59a981c0f39ab 100644
> > --- a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> > +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> > @@ -9,9 +9,6 @@ title: Freescale i.MX PWM controller
> > 
> >  maintainers:
> >    - Philipp Zabel <p.zabel@pengutronix.de>
> > 
> > -allOf:
> > -  - $ref: pwm.yaml#
> > -
> > 
> >  properties:
> >    "#pwm-cells":
> >      description: |
> > 
> > @@ -74,6 +71,23 @@ required:
> >  additionalProperties: false
> > 
> > +allOf:
> > +  - $ref: pwm.yaml#
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: fsl,imx1-pwm
> > +    then:
> > +      properties:
> > +        "#pwm-cells":
> > +          enum: [2]
> 
> Given that arch/arm/boot/dts/nxp/imx/imx1.dtsi has:
> 
> 	pwm: pwm@208000 {
> 		#pwm-cells = <3>;
> 		compatible = "fsl,imx1-pwm";
> 		...
> 
> this looks wrong.

Indeed, something i doesn't match. Checking with [1] section 22.4.1 there are 
no bits regarding output inversion. Also pwm_imx1_apply returns -EINVAL if 
state->polarity != PWM_POLARITY_NORMAL.
So IMO "#pwm-cells = <3>" is wrong for imx1. If fixed to 2, this also matches 
the description for the value of #pwm-cells in imx-pwm.yaml.

Best regards,
Alexander

[1] https://www.nxp.com/docs/en/reference-manual/MC9328MX1RM.pdf

> 
> Best regards
> Uwe


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Re: [PATCH 3/3] arm64: dts: freescale: imx8-ss-dma: Fix #pwm-cells

[Uwe Kleine-König]

[-- Attachment #1.1: Type: text/plain, Size: 1407 bytes --]

Hello,

[Cc -= Philippe Schenker]

On Mon, Nov 06, 2023 at 10:52:05AM +0100, Alexander Stein wrote:
> i.MX8QXP supports inverted PWM output, thus #pwm-cells needs to be set
> to 3.
> 
> Fixes: f1d6a6b991ef9 ("arm64: dts: imx8qxp: add adma_pwm in adma")
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> index ce66d30a4839b..b0bb77150adcc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> @@ -149,7 +149,7 @@ adma_pwm: pwm@5a190000 {
>  		clock-names = "ipg", "per";
>  		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
>  		assigned-clock-rates = <24000000>;
> -		#pwm-cells = <2>;
> +		#pwm-cells = <3>;
>  		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
>  	};

Even without patch #1 this is a good change. There are no usages of the
adma_pwm handle as of today's next. So no consumers need adaption.

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Best regards
Uwe

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Re: [PATCH 1/3] dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells

[Uwe Kleine-König]

[-- Attachment #1.1: Type: text/plain, Size: 2823 bytes --]

On Mon, Nov 06, 2023 at 11:49:19AM +0100, Alexander Stein wrote:
> Hello Uwe,
> 
> Am Montag, 6. November 2023, 11:36:21 CET schrieb Uwe Kleine-König:
> > Hello,
> > 
> > [dropped Philippe Schenker from Cc as his email bounced in the past]
> > 
> > On Mon, Nov 06, 2023 at 10:52:03AM +0100, Alexander Stein wrote:
> > > Only fsl,imx1-pwm comptabile devices use #pwm-cells = <2>. Newer SoCs
> > > supportinverted PWM output, thus #pwm-cells needs to be set to 3.
> > > 
> > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > > ---
> > > 
> > >  .../devicetree/bindings/pwm/imx-pwm.yaml      | 20 ++++++++++++++++---
> > >  1 file changed, 17 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> > > b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml index
> > > c01dff3b7f843..59a981c0f39ab 100644
> > > --- a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> > > +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
> > > @@ -9,9 +9,6 @@ title: Freescale i.MX PWM controller
> > > 
> > >  maintainers:
> > >    - Philipp Zabel <p.zabel@pengutronix.de>
> > > 
> > > -allOf:
> > > -  - $ref: pwm.yaml#
> > > -
> > > 
> > >  properties:
> > >    "#pwm-cells":
> > >      description: |
> > > 
> > > @@ -74,6 +71,23 @@ required:
> > >  additionalProperties: false
> > > 
> > > +allOf:
> > > +  - $ref: pwm.yaml#
> > > +
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            const: fsl,imx1-pwm
> > > +    then:
> > > +      properties:
> > > +        "#pwm-cells":
> > > +          enum: [2]
> > 
> > Given that arch/arm/boot/dts/nxp/imx/imx1.dtsi has:
> > 
> > 	pwm: pwm@208000 {
> > 		#pwm-cells = <3>;
> > 		compatible = "fsl,imx1-pwm";
> > 		...
> > 
> > this looks wrong.
> 
> Indeed, something i doesn't match. Checking with [1] section 22.4.1 there are 
> no bits regarding output inversion. Also pwm_imx1_apply returns -EINVAL if 
> state->polarity != PWM_POLARITY_NORMAL.
> So IMO "#pwm-cells = <3>" is wrong for imx1. If fixed to 2, this also matches 
> the description for the value of #pwm-cells in imx-pwm.yaml.

The reasoning only works in one direction, i.e. if your PWM supports
inversed polarity you need #pwm-cells = <3>. But there no problem in
using 3 cells for a PWM that doesn't support inversed output. Some might
call it unnecessary verboseness, other might call it consistency.

I'd say the right thing to do here is to stick to = 3 and adapt this
patch and the already existing comment in imx-pwm.yaml.

Best regards
Uwe

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Re: [PATCH 1/3] dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells

[Shawn Guo]

On Mon, Nov 06, 2023 at 10:52:03AM +0100, Alexander Stein wrote:
> Only fsl,imx1-pwm comptabile devices use #pwm-cells = <2>. Newer SoCs
> supportinverted PWM output, thus #pwm-cells needs to be set to 3.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

As suggested by Uwe, I picked this up too.

Shawn

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Re: [PATCH 1/3] dt-bindings: pwm: imx-pwm: Add constraints for #pwm-cells

[Shawn Guo]

On Tue, Dec 5, 2023 at 8:36 PM Shawn Guo <shawnguo@kernel.org> wrote:
>
> On Mon, Nov 06, 2023 at 10:52:03AM +0100, Alexander Stein wrote:
> > Only fsl,imx1-pwm comptabile devices use #pwm-cells = <2>. Newer SoCs
> > supportinverted PWM output, thus #pwm-cells needs to be set to 3.
> >
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
>
> As suggested by Uwe, I picked this up too.

Sorry, I picked v2 up actually.

Shawn

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