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[175.34.8.244]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e5a5ecbdd3sm17417165ad.48.2026.10.05.22.44.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Oct 2026 22:44:48 -0700 (PDT) Message-ID: <830e8afc-b208-4972-a45a-32c828c14206@redhat.com> Date: Tue, 6 Oct 2026 15:44:39 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v22 21/23] KVM: arm64: CCA: Support timers in realm RECs To: Suzuki K Poulose , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com, jonathan.cameron@oss.qualcomm.com References: <20261005090754.2140522-1-suzuki.poulose@arm.com> <20261005090754.2140522-22-suzuki.poulose@arm.com> From: Gavin Shan In-Reply-To: <20261005090754.2140522-22-suzuki.poulose@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: bLez87G5EkbiEV28vws5pkZ8LFyUAAUWuB1WM9CJgWs_1791265490 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_224454_682326_0AA6080E X-CRM114-Status: GOOD ( 23.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/5/26 7:07 PM, Suzuki K Poulose wrote: > From: Steven Price > > The RMM keeps track of the timer while the realm REC is running, but on > exit to the normal world KVM is responsible for handling the timers. > > A later patch adds the support for propagating the timer values from the > exit data structure and making sure the values are in sync for KVM. > > Also, RMM doesn't support injecting virtual interrupts backed by Physical > interrupts. So, use the existing software resampling mechanims for Realm ^^^^^^^^^ typo: mechanism > timer interrupts. > > Signed-off-by: Steven Price > Signed-off-by: Suzuki K Poulose > --- > arch/arm64/kvm/arch_timer.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index a45845f4ae4ea..428709f499205 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -56,11 +56,25 @@ static unsigned long kvm_arch_timer_get_irq_flags(void) > return kvm_vgic_global_state.no_hw_deactivation ? VGIC_IRQ_SW_RESAMPLE : 0; > } > > +static unsigned long kvm_realm_timer_get_irq_flags(void) > +{ > + /* > + * RMI_REC_ENTER rejects LRs with the HW bit set, so use the existing > + * software resampling mechanism for Realm timer interrupts. > + */ > + return VGIC_IRQ_SW_RESAMPLE; > +} > + > static const struct irq_ops arch_timer_irq_ops = { > .get_flags = kvm_arch_timer_get_irq_flags, > .get_input_level = kvm_arch_timer_get_input_level, > }; > > +static const struct irq_ops realm_timer_irq_ops = { > + .get_flags = kvm_realm_timer_get_irq_flags, > + .get_input_level = kvm_arch_timer_get_input_level, > +}; > + > static const struct irq_ops arch_timer_irq_ops_vgic_v5 = { > .get_input_level = kvm_arch_timer_get_input_level, > .queue_irq_unlock = vgic_v5_ppi_queue_irq_unlock, > @@ -1617,8 +1631,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) > > get_timer_map(vcpu, &map); > > - ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : > - &arch_timer_irq_ops; > + if (vcpu_is_rec(vcpu)) > + ops = &realm_timer_irq_ops; > + else if (vgic_is_v5(vcpu->kvm)) > + ops = &arch_timer_irq_ops_vgic_v5; > + else > + ops = &arch_timer_irq_ops; > > for (int i = 0; i < nr_timers(vcpu); i++) > kvm_vgic_set_irq_ops(vcpu, timer_irq(vcpu_get_timer(vcpu, i)), ops);