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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260922_075927_140993_43E7E740 X-CRM114-Status: GOOD ( 21.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 9/8/26 09:05, muhammad.nazim.amirul.nazle.asmade@altera.com wrote: > From: Nazim Amirul > > The Agilex5 SoCDK TSN Config2 board uses a GMII-to-RGMII converter > implemented as FPGA soft IP between gmac1 and its PHY. This converter > provides the RGMII TX/RX clock delays, so the MAC interface selector > must be configured for GMII while the PHY is configured without delays. > > Add the "altr,socfpga-stmmac-agilex5-tsn" compatible with dedicated > match .data ops that extend the standard Agilex5 setup: force GMII for > the MAC interface selector and strip delay bits from phy_interface so > the PHY is not configured to add delays already provided by the FPGA > converter. > > Signed-off-by: Nazim Amirul > Reviewed-by: Andrew Lunn Reviewed-by: Maxime Chevallier Maxime > --- > v6: No changes from v5. > v5: Replace of_device_is_compatible() probe check with dedicated > socfpga_agilex5_tsn_gmac_ops via match .data, per Krzysztof > Kozlowski and Dinh Nguyen. > v4: Add Reviewed-by from Andrew Lunn. > > .../ethernet/stmicro/stmmac/dwmac-socfpga.c | 23 ++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c > index 1d7f0a57d288..0632105b420f 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c > @@ -69,12 +69,13 @@ struct socfpga_dwmac { > void __iomem *tse_pcs_base; > void __iomem *sgmii_adapter_base; > bool f2h_ptp_ref_clk; > + phy_interface_t mac_interface; > const struct socfpga_dwmac_ops *ops; > }; > > static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac) > { > - return dwmac->plat_dat->phy_interface; > + return dwmac->mac_interface; > } > > static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable) > @@ -650,6 +651,8 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) > plat_dat->pcs_exit = socfpga_dwmac_pcs_exit; > plat_dat->select_pcs = socfpga_dwmac_select_pcs; > > + dwmac->mac_interface = plat_dat->phy_interface; > + > ops->setup_plat_dat(dwmac); > > return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); > @@ -670,10 +673,28 @@ static const struct socfpga_dwmac_ops socfpga_agilex5_ops = { > .setup_plat_dat = socfpga_agilex5_setup_plat_dat, > }; > > +static void socfpga_agilex5_tsn_gmac_setup_plat_dat(struct socfpga_dwmac *dwmac) > +{ > + struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat; > + > + socfpga_agilex5_setup_plat_dat(dwmac); > + > + /* FPGA converter supplies RGMII delays; MAC uses GMII, PHY gets plain RGMII */ > + dwmac->mac_interface = PHY_INTERFACE_MODE_GMII; > + if (phy_interface_mode_is_rgmii(plat_dat->phy_interface)) > + plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII; > +} > + > +static const struct socfpga_dwmac_ops socfpga_agilex5_tsn_gmac_ops = { > + .set_phy_mode = socfpga_gen10_set_phy_mode, > + .setup_plat_dat = socfpga_agilex5_tsn_gmac_setup_plat_dat, > +}; > + > static const struct of_device_id socfpga_dwmac_match[] = { > { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops }, > { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops }, > { .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops }, > + { .compatible = "altr,socfpga-stmmac-agilex5-tsn", .data = &socfpga_agilex5_tsn_gmac_ops }, > { } > }; > MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);