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[144.49.247.125]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-3ada47f18a2sm2417478a91.0.2026.10.22.10.36.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Oct 2026 10:36:22 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-88c768886a6so83402b3a.2 for ; Thu, 22 Oct 2026 10:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1792690580; x=1793295380; darn=lists.infradead.org; h=content-transfer-encoding:content-type:in-reply-to:autocrypt:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:from:to:cc:subject:date:message-id:reply-to :content-type; bh=aQ9LiTLbh2uxFCSppkL9rHsktv+7lwK3tJuZ2euHX10=; b=K3yi/n+axFqO8GygHFn/J4B79jPrg8I6ujGN1RXuZ0dpGDZy29jhkDpO0nUgSX2sZC ZWU9a4ywz2agzjyuaHdpXEi+Aza3Fcyob+2H/bXPaj84BJBO92UBdRVcgYjyF8KBl2YO nLNd+Q7BihMRN2ycqRtdo2rxIlHmW4yZnfRZE= X-Forwarded-Encrypted: i=1; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261022_103624_688753_60857CB3 X-CRM114-Status: GOOD ( 22.52 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 10/21/26 23:50, Damien Le Moal wrote: > On 2026/10/21 18:55, Florian Fainelli wrote: >> The NSP probe path assumes firmware has enabled the SATA IDM interface >> clock and released the core reset. The downstream iProc config_AHCI() >> sequence explicitly performs both operations before accessing AHCI. >> Without that setup, a cold boot can access an inactive controller. >> >> Map the optional NSP IDM register region and enable the interface clock >> before releasing reset, retaining the downstream settling intervals. >> Perform the sequence at probe and resume before reconfiguring SATA. >> >> Keep the resource optional so older device trees continue to rely on >> firmware initialization. >> >> Fixes: 3ee2e6dcaa35 ("ata: ahci_brcm: Add support for Broadcom NSP SoC") >> Signed-off-by: Florian Fainelli >> --- >> drivers/ata/ahci_brcm.c | 34 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> >> diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c >> index 29be74fedcf0..2ed60806b671 100644 >> --- a/drivers/ata/ahci_brcm.c >> +++ b/drivers/ata/ahci_brcm.c >> @@ -6,7 +6,9 @@ >> */ >> >> #include >> +#include >> #include >> +#include >> #include >> #include >> #include >> @@ -83,6 +85,7 @@ enum brcm_ahci_quirks { >> struct brcm_ahci_priv { >> struct device *dev; >> void __iomem *top_ctrl; >> + void __iomem *idm; >> u32 port_mask; >> u32 quirks; >> enum brcm_ahci_version version; >> @@ -230,6 +233,25 @@ static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv, >> return impl; >> } >> >> +static void brcm_sata_init_idm(struct brcm_ahci_priv *priv) >> +{ >> + u32 data; >> + >> + if (!priv->idm) >> + return; >> + >> + /* Enable the interface clock before taking the SATA core out of reset. */ > > Long line. Please split before 80 chars. > >> + data = readl(priv->idm + BCMA_IOCTL); >> + writel(data | BCMA_IOCTL_CLK, priv->idm + BCMA_IOCTL); >> + readl(priv->idm + BCMA_IOCTL); >> + usleep_range(1000, 2000); >> + >> + data = readl(priv->idm + BCMA_RESET_CTL); >> + writel(data & ~BCMA_RESET_CTL_RESET, priv->idm + BCMA_RESET_CTL); >> + readl(priv->idm + BCMA_RESET_CTL); >> + usleep_range(1000, 2000); >> +} >> + >> static void brcm_sata_init(struct brcm_ahci_priv *priv) >> { >> void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL; >> @@ -369,6 +391,8 @@ static int __maybe_unused brcm_ahci_resume(struct device *dev) >> struct brcm_ahci_priv *priv = hpriv->plat_data; >> int ret = 0; >> >> + brcm_sata_init_idm(priv); >> + >> ret = reset_control_deassert(priv->rcdev_ahci); >> if (ret) >> return ret; >> @@ -453,6 +477,14 @@ static int brcm_ahci_probe(struct platform_device *pdev) >> priv->version = (unsigned long)of_id->data; >> priv->dev = dev; >> >> + /* Older NSP device trees rely on firmware to initialize the IDM. */ >> + if (priv->version == BRCM_SATA_NSP && >> + platform_get_resource_byname(pdev, IORESOURCE_MEM, "idm")) { >> + priv->idm = devm_platform_ioremap_resource_byname(pdev, "idm"); >> + if (IS_ERR(priv->idm)) >> + return PTR_ERR(priv->idm); >> + } >> + >> priv->top_ctrl = devm_platform_ioremap_resource_byname(pdev, "top-ctrl"); >> if (IS_ERR(priv->top_ctrl)) >> return PTR_ERR(priv->top_ctrl); >> @@ -493,6 +525,8 @@ static int brcm_ahci_probe(struct platform_device *pdev) >> if (ret) >> return ret; >> >> + brcm_sata_init_idm(priv); > > Here, this is called *before* the clocks are enabled, but in brcm_ahci_resume(), > brcm_sata_init() -> brcm_sata_init_idm(() is called *after* the clocks are > enabled. Does this matter? The NSP platform does not support suspend/resume but the consistency should be preserved, logically this should be just like during initialization, thanks! -- Florian