[PATCH 0/6] Support for the NPU in Vim3

[PATCH 0/6] Support for the NPU in Vim3

[Tomeu Vizoso]

Hi,

This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
as in the VIM3 board.

The IP is very closeley based on previous Vivante GPUs, so the etnaviv
driver works basically unchanged.

Regards,

Tomeu

Tomeu Vizoso (6):
  dt-bindings: reset: meson-g12a: Add missing NNA reset
  dt-bindings: power: Add NNA power domain
  soc: amlogic: meson-pwrc: Add NNA power domain for A311D
  arm64: dts: meson-g12-common: Add reference to NNA reset to pwrc
  arm64: dts: Add DT node for the VIPNano-QI on the A311D
  drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055

 .../boot/dts/amlogic/meson-g12-common.dtsi    | 15 +++++++--
 .../amlogic/meson-g12b-a311d-khadas-vim3.dts  |  4 +++
 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c        | 31 +++++++++++++++++++
 drivers/soc/amlogic/meson-ee-pwrc.c           | 17 ++++++++++
 include/dt-bindings/power/meson-g12a-power.h  |  1 +
 .../reset/amlogic,meson-g12a-reset.h          |  4 ++-
 6 files changed, 69 insertions(+), 3 deletions(-)

-- 
2.38.1


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[PATCH 1/6] dt-bindings: reset: meson-g12a: Add missing NNA reset

[Tomeu Vizoso]

Doesn't appear in the TRM I have, but it is used by the downstream
galcore driver.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 include/dt-bindings/reset/amlogic,meson-g12a-reset.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
index 6d487c5eba2c..45f6b8a951d0 100644
--- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
@@ -69,7 +69,9 @@
 #define RESET_PARSER_FETCH		72
 #define RESET_CTL			73
 #define RESET_PARSER_TOP		74
-/*					75-77	*/
+/*					75	*/
+#define RESET_NNA			76
+/*					77	*/
 #define RESET_DVALIN			78
 #define RESET_HDMITX			79
 /*					80-95	*/
-- 
2.38.1


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[PATCH 2/6] dt-bindings: power: Add NNA power domain

[Tomeu Vizoso]

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 include/dt-bindings/power/meson-g12a-power.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
index bb5e67a842de..93b03bdd60b7 100644
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ b/include/dt-bindings/power/meson-g12a-power.h
@@ -9,5 +9,6 @@
 
 #define PWRC_G12A_VPU_ID		0
 #define PWRC_G12A_ETH_ID		1
+#define PWRC_G12A_NNA_ID		2
 
 #endif
-- 
2.38.1


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[PATCH 3/6] soc: amlogic: meson-pwrc: Add NNA power domain for A311D

[Tomeu Vizoso]

Based on power initialization sequence in downstream driver.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
index dd5f2a13ceb5..925cfaf50d11 100644
--- a/drivers/soc/amlogic/meson-ee-pwrc.c
+++ b/drivers/soc/amlogic/meson-ee-pwrc.c
@@ -46,6 +46,9 @@
 #define HHI_NANOQ_MEM_PD_REG1		(0x47 << 2)
 #define HHI_VPU_MEM_PD_REG2		(0x4d << 2)
 
+#define G12A_HHI_NANOQ_MEM_PD_REG0	(0x43 << 2)
+#define G12A_HHI_NANOQ_MEM_PD_REG1	(0x44 << 2)
+
 struct meson_ee_pwrc;
 struct meson_ee_pwrc_domain;
 
@@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
 
+static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {	\
+		.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 		\
+		.sleep_mask = BIT(16) | BIT(17),		\
+		.iso_reg = GX_AO_RTI_GEN_PWR_ISO0, 		\
+		.iso_mask = BIT(16) | BIT(17), 			\
+	};
+
 /* Memory PD Domains */
 
 #define VPU_MEMPD(__reg)					\
@@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
 };
 
+static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
+	{ G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff },
+	{ G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff },
+};
+
 #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks)	\
 	{								\
 		.name = __name,						\
@@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
 	[PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
 				     pwrc_ee_is_powered_off, 11, 2),
 	[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
+	[PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
+				    pwrc_ee_is_powered_off),
 };
 
 static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
-- 
2.38.1


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[PATCH 4/6] arm64: dts: meson-g12-common: Add reference to NNA reset to pwrc

[Tomeu Vizoso]

Based on the power sequence in the downstream driver.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 45947c1031c4..fa96fddf4633 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -1625,10 +1625,11 @@ pwrc: power-controller {
 							 <&reset RESET_VDAC>,
 							 <&reset RESET_VDI6>,
 							 <&reset RESET_VENCL>,
-							 <&reset RESET_VID_LOCK>;
+							 <&reset RESET_VID_LOCK>,
+							 <&reset RESET_NNA>;
 						reset-names = "viu", "venc", "vcbus", "bt656",
 							      "rdma", "venci", "vencp", "vdac",
-							      "vdi6", "vencl", "vid_lock";
+							      "vdi6", "vencl", "vid_lock", "nna";
 						clocks = <&clkc CLKID_VPU>,
 							 <&clkc CLKID_VAPB>;
 						clock-names = "vpu", "vapb";
-- 
2.38.1


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[PATCH 5/6] arm64: dts: Add DT node for the VIPNano-QI on the A311D

[Tomeu Vizoso]

This "NPU" is very similar to the Vivante GPUs and Etnaviv works well
with it with just a few small changes.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi      | 10 ++++++++++
 .../boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts  |  4 ++++
 2 files changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index fa96fddf4633..13c79676a356 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/meson-g12a-power.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -2485,4 +2486,13 @@ xtal: xtal-clk {
 		#clock-cells = <0>;
 	};
 
+	npu: npu@ff100000 {
+		compatible = "vivante,gc";
+		reg = <0x0 0xff100000 0x0 0x20000>;
+		interrupts = <0 147 4>;
+		clocks = <&clkc CLKID_NNA_CORE_CLK>,
+			<&clkc CLKID_NNA_AXI_CLK>;
+		clock-names = "core", "bus";
+		power-domains = <&pwrc PWRC_G12A_NNA_ID>;
+	};
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
index 124a80901084..73f3d87dcefd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
@@ -15,6 +15,10 @@ / {
 	compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
 };
 
+&npu {
+	status = "okay";
+};
+
 /*
  * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
  * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-- 
2.38.1


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Re: [PATCH 1/6] dt-bindings: reset: meson-g12a: Add missing NNA reset

[Neil Armstrong]

On 25/11/2022 12:19, Tomeu Vizoso wrote:
> Doesn't appear in the TRM I have, but it is used by the downstream
> galcore driver.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> ---
>   include/dt-bindings/reset/amlogic,meson-g12a-reset.h | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
> index 6d487c5eba2c..45f6b8a951d0 100644
> --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
> +++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
> @@ -69,7 +69,9 @@
>   #define RESET_PARSER_FETCH		72
>   #define RESET_CTL			73
>   #define RESET_PARSER_TOP		74
> -/*					75-77	*/
> +/*					75	*/
> +#define RESET_NNA			76
> +/*					77	*/
>   #define RESET_DVALIN			78
>   #define RESET_HDMITX			79
>   /*					80-95	*/



Acked-by: Neil Armstrong <neil.armstrong@linaro.org>

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Re: [PATCH 2/6] dt-bindings: power: Add NNA power domain

[Neil Armstrong]

On 25/11/2022 12:19, Tomeu Vizoso wrote:
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> ---
>   include/dt-bindings/power/meson-g12a-power.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
> index bb5e67a842de..93b03bdd60b7 100644
> --- a/include/dt-bindings/power/meson-g12a-power.h
> +++ b/include/dt-bindings/power/meson-g12a-power.h
> @@ -9,5 +9,6 @@
>   
>   #define PWRC_G12A_VPU_ID		0
>   #define PWRC_G12A_ETH_ID		1
> +#define PWRC_G12A_NNA_ID		2
>   
>   #endif


Acked-by: Neil Armstrong <neil.armstrong@linaro.org>

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Re: [PATCH 3/6] soc: amlogic: meson-pwrc: Add NNA power domain for A311D

[Neil Armstrong]

On 25/11/2022 12:19, Tomeu Vizoso wrote:
> Based on power initialization sequence in downstream driver.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> ---
>   drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
> index dd5f2a13ceb5..925cfaf50d11 100644
> --- a/drivers/soc/amlogic/meson-ee-pwrc.c
> +++ b/drivers/soc/amlogic/meson-ee-pwrc.c
> @@ -46,6 +46,9 @@
>   #define HHI_NANOQ_MEM_PD_REG1		(0x47 << 2)
>   #define HHI_VPU_MEM_PD_REG2		(0x4d << 2)
>   
> +#define G12A_HHI_NANOQ_MEM_PD_REG0	(0x43 << 2)
> +#define G12A_HHI_NANOQ_MEM_PD_REG1	(0x44 << 2)
> +
>   struct meson_ee_pwrc;
>   struct meson_ee_pwrc_domain;
>   
> @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
>   static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
>   static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
>   
> +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {	\
> +		.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 		\
> +		.sleep_mask = BIT(16) | BIT(17),		\
> +		.iso_reg = GX_AO_RTI_GEN_PWR_ISO0, 		\
> +		.iso_mask = BIT(16) | BIT(17), 			\
> +	};
> +
>   /* Memory PD Domains */
>   
>   #define VPU_MEMPD(__reg)					\
> @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
>   	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
>   };
>   
> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
> +	{ G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff },
> +	{ G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff },

Weird it's not 0xff like on SM1, I looked at the A311D Datasheet and
HHI_NANOQ_MEM_PD_REG0 is 31:0 so 0xffffffff is correct, but
HHI_NANOQ_MEM_PD_REG1 is 23:0 so 0xFFFFFF is the correct value.

Bur please replace with GENMASK(31, 0) and GENMASK(23, 0) to align with the
rest of the code.

> +};
> +
>   #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks)	\
>   	{								\
>   		.name = __name,						\
> @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
>   	[PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
>   				     pwrc_ee_is_powered_off, 11, 2),
>   	[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
> +	[PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
> +				    pwrc_ee_is_powered_off),
>   };
>   
>   static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {

With this fixed:

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>


Thanks,
Neil


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Re: [PATCH 4/6] arm64: dts: meson-g12-common: Add reference to NNA reset to pwrc

[Neil Armstrong]

On 25/11/2022 12:19, Tomeu Vizoso wrote:
> Based on the power sequence in the downstream driver.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> ---
>   arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> index 45947c1031c4..fa96fddf4633 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> @@ -1625,10 +1625,11 @@ pwrc: power-controller {
>   							 <&reset RESET_VDAC>,
>   							 <&reset RESET_VDI6>,
>   							 <&reset RESET_VENCL>,
> -							 <&reset RESET_VID_LOCK>;
> +							 <&reset RESET_VID_LOCK>,
> +							 <&reset RESET_NNA>;

I think this should go in the npu node instead, those are for the VPU power domain.

>   						reset-names = "viu", "venc", "vcbus", "bt656",
>   							      "rdma", "venci", "vencp", "vdac",
> -							      "vdi6", "vencl", "vid_lock";
> +							      "vdi6", "vencl", "vid_lock", "nna";
>   						clocks = <&clkc CLKID_VPU>,
>   							 <&clkc CLKID_VAPB>;
>   						clock-names = "vpu", "vapb";


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