From: <Conor.Dooley@microchip.com>
To: <jrtc27@jrtc27.com>
Cc: <palmer@dabbelt.com>, <palmer@rivosinc.com>,
<atishp@atishpatra.org>, <anup@brainfault.org>, <will@kernel.org>,
<mark.rutland@arm.com>, <paul.walmsley@sifive.com>,
<aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] perf: riscv: fix broken build due to struct redefinition
Date: Fri, 12 Aug 2022 14:19:54 +0000 [thread overview]
Message-ID: <84e4739c-0197-f9d9-5529-24f6037c85fa@microchip.com> (raw)
In-Reply-To: <2055040C-D443-47FD-B6E2-C4C6B3E600B4@jrtc27.com>
On 12/08/2022 15:13, Jessica Clarke wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 12 Aug 2022, at 14:51, Conor Dooley <conor.dooley@microchip.com> wrote:
>>
>> Building riscv/for-next produces following error:
>> drivers/perf/riscv_pmu_sbi.c:44:7: error: redefinition of 'sbi_pmu_ctr_info'
>> union sbi_pmu_ctr_info {
>> ^
>> arch/riscv/include/asm/sbi.h:125:7: note: previous definition is here
>> union sbi_pmu_ctr_info {
>>
>> This appears to have been caused by a merge conflict resolution between
>> riscv/for-next & riscv/fixes, causing the struct define not being
>
> union, not struct
autopilot, thanks :)
>
> Jess
>
>> properly moved to its header.
>>
>> Fixes: 9a7ccac63f9c ("perf: riscv_pmu{,_sbi}: Miscallenous improvement & fixes")
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> drivers/perf/riscv_pmu_sbi.c | 14 --------------
>> 1 file changed, 14 deletions(-)
>>
>> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
>> index e7c6fecbf061..6f6681bbfd36 100644
>> --- a/drivers/perf/riscv_pmu_sbi.c
>> +++ b/drivers/perf/riscv_pmu_sbi.c
>> @@ -41,20 +41,6 @@ static const struct attribute_group *riscv_pmu_attr_groups[] = {
>> NULL,
>> };
>>
>> -union sbi_pmu_ctr_info {
>> - unsigned long value;
>> - struct {
>> - unsigned long csr:12;
>> - unsigned long width:6;
>> -#if __riscv_xlen == 32
>> - unsigned long reserved:13;
>> -#else
>> - unsigned long reserved:45;
>> -#endif
>> - unsigned long type:1;
>> - };
>> -};
>> -
>> /*
>> * RISC-V doesn't have hetergenous harts yet. This need to be part of
>> * per_cpu in case of harts with different pmu counters
>> --
>> 2.36.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
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next prev parent reply other threads:[~2022-08-12 14:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 13:51 [PATCH] perf: riscv: fix broken build due to struct redefinition Conor Dooley
2022-08-12 14:13 ` Jessica Clarke
2022-08-12 14:19 ` Conor.Dooley [this message]
2022-08-12 22:33 ` Palmer Dabbelt
2022-08-12 22:36 ` Conor.Dooley
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