[PATCH v1 0/7] drm/rockchip: Add MIPI DSI support for RK3368

[PATCH v1 0/7] drm/rockchip: Add MIPI DSI support for RK3368

[WeiHao Li]

This series adds MIPI DSI support for the Rockchip RK3368 SoC, enabling
native display connectivity through the MIPI DSI host controller and
PHY. The changes span multiple subsystems, including clock control,
DRM/VOP integration, DSI controller binding, and PHY driver updates.

Key changes:
  - Update the Rockchip MIPI DSI PHY driver to preperly handle RK3368
    phy initialization.
  - Add missing lut_size of vop_data for RK3368.
  - Add missing clock ID SCLK_MIPIDSI_24M to the RK3368 CRU driver,
    which is required for enabling the 24MHz reference clock.
  - Add MIPI DSI node to rk3368.dtsi with correct clocks, resets,
    and register mappings.

These changes were tested on a RK3368-based board with a MIPI DSI
panel [1]. The display boots successfully with console output.

[1] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368

Tested-by: WeiHao Li <cn.liweihao@gmail.com>
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

WeiHao Li (7):
  drm/rockchip: dsi: Add support for RK3368
  drm/rockchip: vop: add lut_size for RK3368 vop_data
  dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
  clk: rockchip: use clock ids for SCLK_MIPIDSI_24M on rk3368
  ARM: dts: rockchip: Add display subsystem for RK3368
  ARM: dts: rockchip: Add D-PHY for RK3368
  ARM: dts: rockchip: Add DSI for RK3368

 arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 79 +++++++++++++++++++
 drivers/clk/rockchip/clk-rk3368.c             |  2 +-
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c   |  1 +
 include/dt-bindings/clock/rk3368-cru.h        |  1 +
 5 files changed, 102 insertions(+), 1 deletion(-)

-- 
2.47.2

[PATCH v1 1/7] drm/rockchip: dsi: Add support for RK3368

[WeiHao Li]

RK3368 has DesignWare MIPI DSI controller and an external inno D-PHY.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 3398160ad..5d76e3e04 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -162,6 +162,11 @@
 #define RK3288_DSI0_LCDC_SEL		BIT(6)
 #define RK3288_DSI1_LCDC_SEL		BIT(9)
 
+#define RK3368_GRF_SOC_CON7		0x41c
+#define RK3368_DSI_FORCETXSTOPMODE	(0xf << 7)
+#define RK3368_DSI_FORCERXMODE		BIT(6)
+#define RK3368_DSI_TURNDISABLE		BIT(5)
+
 #define RK3399_GRF_SOC_CON20		0x6250
 #define RK3399_DSI0_LCDC_SEL		BIT(0)
 #define RK3399_DSI1_LCDC_SEL		BIT(4)
@@ -1530,6 +1535,18 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = {
+	{
+		.reg = 0xff960000,
+		.lanecfg1_grf_reg = RK3368_GRF_SOC_CON7,
+		.lanecfg1 = HIWORD_UPDATE(0, RK3368_DSI_TURNDISABLE |
+						RK3368_DSI_FORCETXSTOPMODE |
+						RK3368_DSI_FORCERXMODE),
+		.max_data_lanes = 4,
+	},
+	{ /* sentinel */ }
+};
+
 static int rk3399_dphy_tx1rx1_init(struct phy *phy)
 {
 	struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
@@ -1693,6 +1710,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
 	}, {
 	 .compatible = "rockchip,rk3288-mipi-dsi",
 	 .data = &rk3288_chip_data,
+	}, {
+	 .compatible = "rockchip,rk3368-mipi-dsi",
+	 .data = &rk3368_chip_data,
 	}, {
 	 .compatible = "rockchip,rk3399-mipi-dsi",
 	 .data = &rk3399_chip_data,
-- 
2.47.2

Re: [PATCH v1 1/7] drm/rockchip: dsi: Add support for RK3368

[Heiko Stuebner]

Hi,

Am Sonntag, 31. August 2025, 12:48:49 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> RK3368 has DesignWare MIPI DSI controller and an external inno D-PHY.
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

as a general remark, this patch will likely need to wait for 6.18-rc1,
because a big update of the HIWORD_MASK macros was merged [0].

So introducing a new user now would cause havok :-) .

Also when sending a v2, please base it on top of that changeset, or
just take linux-next [1] as a base.

Also in a separate patch, please add the needed rk3368 entry to the
devicetree binding [2], this will pacify the bot that checked your
devicetree changes :-) .

Please also make sure that relevant additions to the lists below
are made (the binding contains specific settings for some controllers
furter below) .


Heiko


[0] https://lore.kernel.org/linux-rockchip/20250825-byeword-update-v3-0-947b841cdb29@collabora.com/
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml

> ---
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index 3398160ad..5d76e3e04 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -162,6 +162,11 @@
>  #define RK3288_DSI0_LCDC_SEL		BIT(6)
>  #define RK3288_DSI1_LCDC_SEL		BIT(9)
>  
> +#define RK3368_GRF_SOC_CON7		0x41c
> +#define RK3368_DSI_FORCETXSTOPMODE	(0xf << 7)
> +#define RK3368_DSI_FORCERXMODE		BIT(6)
> +#define RK3368_DSI_TURNDISABLE		BIT(5)
> +
>  #define RK3399_GRF_SOC_CON20		0x6250
>  #define RK3399_DSI0_LCDC_SEL		BIT(0)
>  #define RK3399_DSI1_LCDC_SEL		BIT(4)
> @@ -1530,6 +1535,18 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = {
> +	{
> +		.reg = 0xff960000,
> +		.lanecfg1_grf_reg = RK3368_GRF_SOC_CON7,
> +		.lanecfg1 = HIWORD_UPDATE(0, RK3368_DSI_TURNDISABLE |
> +						RK3368_DSI_FORCETXSTOPMODE |
> +						RK3368_DSI_FORCERXMODE),
> +		.max_data_lanes = 4,
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static int rk3399_dphy_tx1rx1_init(struct phy *phy)
>  {
>  	struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
> @@ -1693,6 +1710,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
>  	}, {
>  	 .compatible = "rockchip,rk3288-mipi-dsi",
>  	 .data = &rk3288_chip_data,
> +	}, {
> +	 .compatible = "rockchip,rk3368-mipi-dsi",
> +	 .data = &rk3368_chip_data,
>  	}, {
>  	 .compatible = "rockchip,rk3399-mipi-dsi",
>  	 .data = &rk3399_chip_data,
> 

Re: [PATCH v1 1/7] drm/rockchip: dsi: Add support for RK3368

[李维豪]

Hi,

Heiko Stuebner <heiko@sntech.de> 于2025年9月3日周三 20:07写道：
>
> as a general remark, this patch will likely need to wait for 6.18-rc1,
> because a big update of the HIWORD_MASK macros was merged [0].
>
> So introducing a new user now would cause havok :-) .
>
> Also when sending a v2, please base it on top of that changeset, or
> just take linux-next [1] as a base.
>
> Also in a separate patch, please add the needed rk3368 entry to the
> devicetree binding [2], this will pacify the bot that checked your
> devicetree changes :-) .
>
> Please also make sure that relevant additions to the lists below
> are made (the binding contains specific settings for some controllers
> furter below) .
>

Got it. I'll rebase my patch serial to linux-next tree and test it
before sending v2, and I will also add the necessary commit
description and device tree binding information.

Yours,
Weihao

[PATCH v1 2/7] drm/rockchip: vop: add lut_size for RK3368 vop_data

[WeiHao Li]

VOP driver need a correct lut_size to work normally.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index d1f788763..219f8c2fa 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -880,6 +880,7 @@ static const struct vop_data rk3368_vop = {
 	.win = rk3368_vop_win_data,
 	.win_size = ARRAY_SIZE(rk3368_vop_win_data),
 	.max_output = { 4096, 2160 },
+	.lut_size = 1024,
 };
 
 static const struct vop_intr rk3366_vop_intr = {
-- 
2.47.2

Re: [PATCH v1 2/7] drm/rockchip: vop: add lut_size for RK3368 vop_data

[Heiko Stuebner]

Hi,

Am Sonntag, 31. August 2025, 12:48:50 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> VOP driver need a correct lut_size to work normally.

please add a comment where that value is coming from.
Because the vop in the vendor kernel is so vastly different.


Thanks
Heiko

> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> ---
>  drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> index d1f788763..219f8c2fa 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> @@ -880,6 +880,7 @@ static const struct vop_data rk3368_vop = {
>  	.win = rk3368_vop_win_data,
>  	.win_size = ARRAY_SIZE(rk3368_vop_win_data),
>  	.max_output = { 4096, 2160 },
> +	.lut_size = 1024,
>  };
>  
>  static const struct vop_intr rk3366_vop_intr = {
> 

[PATCH v1 3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M

[WeiHao Li]

Add a clock id for mipi dsi reference clock, mipi dsi node used it.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 include/dt-bindings/clock/rk3368-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index ebae3cbf8..b951e2906 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -72,6 +72,7 @@
 #define SCLK_SFC		126
 #define SCLK_MAC		127
 #define SCLK_MACREF_OUT		128
+#define SCLK_MIPIDSI_24M	129
 #define SCLK_TIMER10		133
 #define SCLK_TIMER11		134
 #define SCLK_TIMER12		135
-- 
2.47.2

Re: [PATCH v1 3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M

[Heiko Stübner]

Hi,
Am Sonntag, 31. August 2025, 12:48:51 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> Add a clock id for mipi dsi reference clock, mipi dsi node used it.
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

you missed a number of devicetree maintainers, Rob thankfully does
not need to do this on his own anymore.

so please get the appropriate list of maintainers via scripts/get_maintainer.pl

Change itself looks fine though.

Heiko

> ---
>  include/dt-bindings/clock/rk3368-cru.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> index ebae3cbf8..b951e2906 100644
> --- a/include/dt-bindings/clock/rk3368-cru.h
> +++ b/include/dt-bindings/clock/rk3368-cru.h
> @@ -72,6 +72,7 @@
>  #define SCLK_SFC		126
>  #define SCLK_MAC		127
>  #define SCLK_MACREF_OUT		128
> +#define SCLK_MIPIDSI_24M	129
>  #define SCLK_TIMER10		133
>  #define SCLK_TIMER11		134
>  #define SCLK_TIMER12		135
> 

Re: [PATCH v1 3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M

[李维豪]

Hi Heiko,

Thanks for your review.

I actually used script to get the maintainer list, but I was not sure
whether I should send-to or cc every maintainer, so I consulted the
AI, and the AI said to try not to do so because it might be considered
noise email, and only send it to the main maintainers.

Should I cc all the devicetree maintainers with the next patches?

Best regards,
WeiHao

Heiko Stübner <heiko@sntech.de> 于2025年8月31日周日 23:00写道：
>
> Hi,
> Am Sonntag, 31. August 2025, 12:48:51 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> > Add a clock id for mipi dsi reference clock, mipi dsi node used it.
> >
> > Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
>
> you missed a number of devicetree maintainers, Rob thankfully does
> not need to do this on his own anymore.
>
> so please get the appropriate list of maintainers via scripts/get_maintainer.pl
>
> Change itself looks fine though.
>
> Heiko
>
> > ---
> >  include/dt-bindings/clock/rk3368-cru.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> > index ebae3cbf8..b951e2906 100644
> > --- a/include/dt-bindings/clock/rk3368-cru.h
> > +++ b/include/dt-bindings/clock/rk3368-cru.h
> > @@ -72,6 +72,7 @@
> >  #define SCLK_SFC             126
> >  #define SCLK_MAC             127
> >  #define SCLK_MACREF_OUT              128
> > +#define SCLK_MIPIDSI_24M     129
> >  #define SCLK_TIMER10         133
> >  #define SCLK_TIMER11         134
> >  #define SCLK_TIMER12         135
> >
>
>
>
>

Re: [PATCH v1 3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M

[Heiko Stuebner]

Hi,

Am Montag, 1. September 2025, 02:17:00 Mitteleuropäische Sommerzeit schrieb 李维豪:
> I actually used script to get the maintainer list, but I was not sure
> whether I should send-to or cc every maintainer, so I consulted the
> AI, and the AI said to try not to do so because it might be considered
> noise email, and only send it to the main maintainers.

please don't top-post :-)
https://docs.kernel.org/process/submitting-patches.html#use-trimmed-interleaved-replies-in-email-discussions


> Should I cc all the devicetree maintainers with the next patches?

Looks like we did get an Ack still with even only one maintainer listed,
so don't need a resend ... but yeah, please include people listed as
direct maintainers in the future.

Workflows differ, so when submitting a patch you can't know if maintainers
work from patchwork or directly from their inbox.

So it's safer to include more people than not enough :-)

Some trimming of the list can be done though, for example your drm patches
would list the core drm maintainers who most likely do not really care
about individual driver patches ;-) .

get_maintainers.pl thankfully does list the role, so you can decide based
on that.


Heiko


> Best regards,
> WeiHao
> 
> Heiko Stübner <heiko@sntech.de> 于2025年8月31日周日 23:00写道：
> >
> > Hi,
> > Am Sonntag, 31. August 2025, 12:48:51 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> > > Add a clock id for mipi dsi reference clock, mipi dsi node used it.
> > >
> > > Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> >
> > you missed a number of devicetree maintainers, Rob thankfully does
> > not need to do this on his own anymore.
> >
> > so please get the appropriate list of maintainers via scripts/get_maintainer.pl
> >
> > Change itself looks fine though.
> >
> > Heiko
> >
> > > ---
> > >  include/dt-bindings/clock/rk3368-cru.h | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> > > index ebae3cbf8..b951e2906 100644
> > > --- a/include/dt-bindings/clock/rk3368-cru.h
> > > +++ b/include/dt-bindings/clock/rk3368-cru.h
> > > @@ -72,6 +72,7 @@
> > >  #define SCLK_SFC             126
> > >  #define SCLK_MAC             127
> > >  #define SCLK_MACREF_OUT              128
> > > +#define SCLK_MIPIDSI_24M     129
> > >  #define SCLK_TIMER10         133
> > >  #define SCLK_TIMER11         134
> > >  #define SCLK_TIMER12         135
> > >
> >
> >
> >
> >
> 

Re: [PATCH v1 3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M

[李维豪]

Hi,

Heiko Stuebner <heiko@sntech.de> 于2025年9月2日周二 14:49写道：
>
> Workflows differ, so when submitting a patch you can't know if maintainers
> work from patchwork or directly from their inbox.
>
> So it's safer to include more people than not enough :-)
>
> Some trimming of the list can be done though, for example your drm patches
> would list the core drm maintainers who most likely do not really care
> about individual driver patches ;-) .
>
> get_maintainers.pl thankfully does list the role, so you can decide based
> on that.
>

Thank you for your patient reply. I understand now, and I'll try to do
better next time.

yours,
WeiHao

Re: [PATCH v1 3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M

[Rob Herring (Arm)]

On Sun, 31 Aug 2025 18:48:51 +0800, WeiHao Li wrote:
> Add a clock id for mipi dsi reference clock, mipi dsi node used it.
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> ---
>  include/dt-bindings/clock/rk3368-cru.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v1 4/7] clk: rockchip: use clock ids for SCLK_MIPIDSI_24M on rk3368

[WeiHao Li]

Export the clocks via the newly added clock-ids.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 04391e4e2..95e6996ad 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -526,7 +526,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 			RK3368_CLKGATE_CON(3), 1, GFLAGS),
 
-	GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
+	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
 
 	/*
 	 * Clock-Architecture Diagram 4
-- 
2.47.2

[PATCH v1 5/7] ARM: dts: rockchip: Add display subsystem for RK3368

[WeiHao Li]

Add vop and display-subsystem nodes to RK3368's device tree.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 26 ++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 73618df7a..0e47bf59a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -858,6 +858,32 @@ vop_mmu: iommu@ff930300 {
 		status = "disabled";
 	};
 
+	vop: vop@ff930000 {
+		compatible = "rockchip,rk3368-vop";
+		reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
+		reg-names = "regs", "gamma_lut";
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+		assigned-clock-rates = <400000000>, <200000000>;
+		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+		reset-names = "axi", "ahb", "dclk";
+		iommus = <&vop_mmu>;
+		status = "disabled";
+
+		vop_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	display_subsystem: display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+		status = "disabled";
+	};
+
 	hevc_mmu: iommu@ff9a0440 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff9a0440 0x0 0x40>,
-- 
2.47.2

Re: [PATCH v1 5/7] ARM: dts: rockchip: Add display subsystem for RK3368

[Heiko Stübner]

Hi,

Am Sonntag, 31. August 2025, 12:48:53 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> Add vop and display-subsystem nodes to RK3368's device tree.
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

please use the appropriate patch prefix. For arm64 this should be
arm64: dts: rockchip:

The one you're using is from the arm32 side.

Also please sort things appropriately both node-position and order of
properties inside nodes, see
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst


Heiko

> ---
>  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 26 ++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index 73618df7a..0e47bf59a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -858,6 +858,32 @@ vop_mmu: iommu@ff930300 {
>  		status = "disabled";
>  	};
>  
> +	vop: vop@ff930000 {
> +		compatible = "rockchip,rk3368-vop";
> +		reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
> +		reg-names = "regs", "gamma_lut";
> +		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
> +		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> +		assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
> +		assigned-clock-rates = <400000000>, <200000000>;
> +		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
> +		reset-names = "axi", "ahb", "dclk";
> +		iommus = <&vop_mmu>;
> +		status = "disabled";
> +
> +		vop_out: port {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	display_subsystem: display-subsystem {
> +		compatible = "rockchip,display-subsystem";
> +		ports = <&vop_out>;
> +		status = "disabled";
> +	};
> +
>  	hevc_mmu: iommu@ff9a0440 {
>  		compatible = "rockchip,iommu";
>  		reg = <0x0 0xff9a0440 0x0 0x40>,
> 

Re: [PATCH v1 5/7] ARM: dts: rockchip: Add display subsystem for RK3368

[李维豪]

Hi

Sorry about that, I didn't notice this before, I will adjust it
according to the documentation.

Best regards,
WeiHao

Heiko Stübner <heiko@sntech.de> 于2025年8月31日周日 23:04写道：

>
> Hi,
>
> Am Sonntag, 31. August 2025, 12:48:53 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> > Add vop and display-subsystem nodes to RK3368's device tree.
> >
> > Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
>
> please use the appropriate patch prefix. For arm64 this should be
> arm64: dts: rockchip:
>
> The one you're using is from the arm32 side.
>
> Also please sort things appropriately both node-position and order of
> properties inside nodes, see
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst
>
>
> Heiko
>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 26 ++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > index 73618df7a..0e47bf59a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > @@ -858,6 +858,32 @@ vop_mmu: iommu@ff930300 {
> >               status = "disabled";
> >       };
> >
> > +     vop: vop@ff930000 {
> > +             compatible = "rockchip,rk3368-vop";
> > +             reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
> > +             reg-names = "regs", "gamma_lut";
> > +             interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> > +             clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
> > +             clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> > +             assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
> > +             assigned-clock-rates = <400000000>, <200000000>;
> > +             resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
> > +             reset-names = "axi", "ahb", "dclk";
> > +             iommus = <&vop_mmu>;
> > +             status = "disabled";
> > +
> > +             vop_out: port {
> > +                     #address-cells = <1>;
> > +                     #size-cells = <0>;
> > +             };
> > +     };
> > +
> > +     display_subsystem: display-subsystem {
> > +             compatible = "rockchip,display-subsystem";
> > +             ports = <&vop_out>;
> > +             status = "disabled";
> > +     };
> > +
> >       hevc_mmu: iommu@ff9a0440 {
> >               compatible = "rockchip,iommu";
> >               reg = <0x0 0xff9a0440 0x0 0x40>,
> >
>
>
>
>

[PATCH v1 6/7] ARM: dts: rockchip: Add D-PHY for RK3368

[WeiHao Li]

RK3368 has a InnoSilicon D-PHY which supports DSI/LVDS/TTL with maximum
trasnfer rate of 1 Gbps per lane.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 0e47bf59a..674a3676d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -884,6 +884,20 @@ display_subsystem: display-subsystem {
 		status = "disabled";
 	};
 
+	video_phy: video-phy@ff968000 {
+		compatible = "rockchip,rk3368-dsi-dphy";
+		reg = <0x0 0xff968000 0x0 0x4000>,
+		      <0x0 0xff960000 0x0 0x4000>;
+		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
+			 <&cru PCLK_MIPI_DSI0>;
+		clock-names = "ref", "pclk", "pclk_host";
+		#clock-cells = <0>;
+		resets = <&cru SRST_MIPIDPHYTX>;
+		reset-names = "apb";
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
 	hevc_mmu: iommu@ff9a0440 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff9a0440 0x0 0x40>,
-- 
2.47.2

Re: [PATCH v1 6/7] ARM: dts: rockchip: Add D-PHY for RK3368

[Heiko Stübner]

Am Sonntag, 31. August 2025, 12:48:54 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> RK3368 has a InnoSilicon D-PHY which supports DSI/LVDS/TTL with maximum
> trasnfer rate of 1 Gbps per lane.
> 
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index 0e47bf59a..674a3676d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -884,6 +884,20 @@ display_subsystem: display-subsystem {
>  		status = "disabled";
>  	};
>  
> +	video_phy: video-phy@ff968000 {

I think the node should be something like
dsi_dphy: phy@ff968000


> +		compatible = "rockchip,rk3368-dsi-dphy";
> +		reg = <0x0 0xff968000 0x0 0x4000>,
> +		      <0x0 0xff960000 0x0 0x4000>;
> +		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
> +			 <&cru PCLK_MIPI_DSI0>;
> +		clock-names = "ref", "pclk", "pclk_host";
> +		#clock-cells = <0>;
> +		resets = <&cru SRST_MIPIDPHYTX>;
> +		reset-names = "apb";
> +		#phy-cells = <0>;
> +		status = "disabled";
> +	};
> +
>  	hevc_mmu: iommu@ff9a0440 {
>  		compatible = "rockchip,iommu";
>  		reg = <0x0 0xff9a0440 0x0 0x40>,
> 

Re: [PATCH v1 6/7] ARM: dts: rockchip: Add D-PHY for RK3368

[李维豪]

Hi,

This phy is a MIPI_DSI/LVDS/TTL combo phy.

maybe it be better to use dphy: phy@ff968000?

Best regards,
WeiHao

Heiko Stübner <heiko@sntech.de> 于2025年8月31日周日 23:06写道：

>
> Am Sonntag, 31. August 2025, 12:48:54 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> > RK3368 has a InnoSilicon D-PHY which supports DSI/LVDS/TTL with maximum
> > trasnfer rate of 1 Gbps per lane.
> >
> > Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > index 0e47bf59a..674a3676d 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > @@ -884,6 +884,20 @@ display_subsystem: display-subsystem {
> >               status = "disabled";
> >       };
> >
> > +     video_phy: video-phy@ff968000 {
>
> I think the node should be something like
> dsi_dphy: phy@ff968000
>
>
> > +             compatible = "rockchip,rk3368-dsi-dphy";
> > +             reg = <0x0 0xff968000 0x0 0x4000>,
> > +                   <0x0 0xff960000 0x0 0x4000>;
> > +             clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
> > +                      <&cru PCLK_MIPI_DSI0>;
> > +             clock-names = "ref", "pclk", "pclk_host";
> > +             #clock-cells = <0>;
> > +             resets = <&cru SRST_MIPIDPHYTX>;
> > +             reset-names = "apb";
> > +             #phy-cells = <0>;
> > +             status = "disabled";
> > +     };
> > +
> >       hevc_mmu: iommu@ff9a0440 {
> >               compatible = "rockchip,iommu";
> >               reg = <0x0 0xff9a0440 0x0 0x40>,
> >
>
>
>
>

[PATCH v1 7/7] ARM: dts: rockchip: Add DSI for RK3368

[WeiHao Li]

Add the Designware MIPI DSI controller and it's port nodes.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 39 ++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 674a3676d..5226b7e6f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -875,6 +875,11 @@ vop: vop@ff930000 {
 		vop_out: port {
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			vop_out_dsi: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&dsi_in_vop>;
+			};
 		};
 	};
 
@@ -884,6 +889,40 @@ display_subsystem: display-subsystem {
 		status = "disabled";
 	};
 
+	mipi_dsi: mipi-dsi@ff960000 {
+		compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x0 0xff960000 0x0 0x4000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_MIPI_DSI0>;
+		clock-names = "pclk";
+		resets = <&cru SRST_MIPIDSI0>;
+		reset-names = "apb";
+		phys = <&video_phy>;
+		phy-names = "dphy";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in: port@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dsi_in_vop: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vop_out_dsi>;
+				};
+			};
+
+			mipi_out: port@1 {
+				reg = <1>;
+			};
+
+		};
+	};
+
 	video_phy: video-phy@ff968000 {
 		compatible = "rockchip,rk3368-dsi-dphy";
 		reg = <0x0 0xff968000 0x0 0x4000>,
-- 
2.47.2

Re: [PATCH v1 0/7] drm/rockchip: Add MIPI DSI support for RK3368

[Heiko Stübner]

Hi,

Am Sonntag, 31. August 2025, 12:48:48 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> This series adds MIPI DSI support for the Rockchip RK3368 SoC, enabling
> native display connectivity through the MIPI DSI host controller and
> PHY. The changes span multiple subsystems, including clock control,
> DRM/VOP integration, DSI controller binding, and PHY driver updates.
> 
> Key changes:
>   - Update the Rockchip MIPI DSI PHY driver to preperly handle RK3368
>     phy initialization.

which patch is doing this, because I don't see any phy-related change

>   - Add missing lut_size of vop_data for RK3368.
>   - Add missing clock ID SCLK_MIPIDSI_24M to the RK3368 CRU driver,
>     which is required for enabling the 24MHz reference clock.
>   - Add MIPI DSI node to rk3368.dtsi with correct clocks, resets,
>     and register mappings.
> 
> These changes were tested on a RK3368-based board with a MIPI DSI
> panel [1]. The display boots successfully with console output.
> 
> [1] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368

Do you plan on submitting this board to mainline?
Because having an actual user of the code you're adding would
be really really nice.

Thanks
Heiko

> 
> Tested-by: WeiHao Li <cn.liweihao@gmail.com>
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> 
> WeiHao Li (7):
>   drm/rockchip: dsi: Add support for RK3368
>   drm/rockchip: vop: add lut_size for RK3368 vop_data
>   dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
>   clk: rockchip: use clock ids for SCLK_MIPIDSI_24M on rk3368
>   ARM: dts: rockchip: Add display subsystem for RK3368
>   ARM: dts: rockchip: Add D-PHY for RK3368
>   ARM: dts: rockchip: Add DSI for RK3368
> 
>  arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 79 +++++++++++++++++++
>  drivers/clk/rockchip/clk-rk3368.c             |  2 +-
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++
>  drivers/gpu/drm/rockchip/rockchip_vop_reg.c   |  1 +
>  include/dt-bindings/clock/rk3368-cru.h        |  1 +
>  5 files changed, 102 insertions(+), 1 deletion(-)
> 
> 

Re: [PATCH v1 0/7] drm/rockchip: Add MIPI DSI support for RK3368

[李维豪]

Hi,

Heiko Stübner <heiko@sntech.de> 于2025年8月31日周日 23:10写道：

>
> Hi,
>
> Am Sonntag, 31. August 2025, 12:48:48 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> > This series adds MIPI DSI support for the Rockchip RK3368 SoC, enabling
> > native display connectivity through the MIPI DSI host controller and
> > PHY. The changes span multiple subsystems, including clock control,
> > DRM/VOP integration, DSI controller binding, and PHY driver updates.
> >
> > Key changes:
> >   - Update the Rockchip MIPI DSI PHY driver to preperly handle RK3368
> >     phy initialization.
>
> which patch is doing this, because I don't see any phy-related change
>

The first patch, changes for dw-mipi-dsi-rockchip.c, some settings for
mipi dphy.

Maybe I should adjust the description, it's a bit unclear.

> >   - Add missing lut_size of vop_data for RK3368.
> >   - Add missing clock ID SCLK_MIPIDSI_24M to the RK3368 CRU driver,
> >     which is required for enabling the 24MHz reference clock.
> >   - Add MIPI DSI node to rk3368.dtsi with correct clocks, resets,
> >     and register mappings.
> >
> > These changes were tested on a RK3368-based board with a MIPI DSI
> > panel [1]. The display boots successfully with console output.
> >
> > [1] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368
>
> Do you plan on submitting this board to mainline?
> Because having an actual user of the code you're adding would
> be really really nice.
>

I'd be happy to submit this board support.

However, after searching for a while, I couldn't find the manufacturer
information of this device and mipi dsi panel. I am not sure whether
the devicetree support of unknown manufacturers allows submission to
mainline.


> Thanks
> Heiko
>
> >
> > Tested-by: WeiHao Li <cn.liweihao@gmail.com>
> > Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> >
> > WeiHao Li (7):
> >   drm/rockchip: dsi: Add support for RK3368
> >   drm/rockchip: vop: add lut_size for RK3368 vop_data
> >   dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
> >   clk: rockchip: use clock ids for SCLK_MIPIDSI_24M on rk3368
> >   ARM: dts: rockchip: Add display subsystem for RK3368
> >   ARM: dts: rockchip: Add D-PHY for RK3368
> >   ARM: dts: rockchip: Add DSI for RK3368
> >
> >  arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 79 +++++++++++++++++++
> >  drivers/clk/rockchip/clk-rk3368.c             |  2 +-
> >  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++
> >  drivers/gpu/drm/rockchip/rockchip_vop_reg.c   |  1 +
> >  include/dt-bindings/clock/rk3368-cru.h        |  1 +
> >  5 files changed, 102 insertions(+), 1 deletion(-)
> >
> >
>
>
>
>

Best regards,
WeiHao

Re: [PATCH v1 0/7] drm/rockchip: Add MIPI DSI support for RK3368

[Rob Herring (Arm)]

On Sun, 31 Aug 2025 18:48:48 +0800, WeiHao Li wrote:
> This series adds MIPI DSI support for the Rockchip RK3368 SoC, enabling
> native display connectivity through the MIPI DSI host controller and
> PHY. The changes span multiple subsystems, including clock control,
> DRM/VOP integration, DSI controller binding, and PHY driver updates.
> 
> Key changes:
>   - Update the Rockchip MIPI DSI PHY driver to preperly handle RK3368
>     phy initialization.
>   - Add missing lut_size of vop_data for RK3368.
>   - Add missing clock ID SCLK_MIPIDSI_24M to the RK3368 CRU driver,
>     which is required for enabling the 24MHz reference clock.
>   - Add MIPI DSI node to rk3368.dtsi with correct clocks, resets,
>     and register mappings.
> 
> These changes were tested on a RK3368-based board with a MIPI DSI
> panel [1]. The display boots successfully with console output.
> 
> [1] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368
> 
> Tested-by: WeiHao Li <cn.liweihao@gmail.com>
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> 
> WeiHao Li (7):
>   drm/rockchip: dsi: Add support for RK3368
>   drm/rockchip: vop: add lut_size for RK3368 vop_data
>   dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
>   clk: rockchip: use clock ids for SCLK_MIPIDSI_24M on rk3368
>   ARM: dts: rockchip: Add display subsystem for RK3368
>   ARM: dts: rockchip: Add D-PHY for RK3368
>   ARM: dts: rockchip: Add DSI for RK3368
> 
>  arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 79 +++++++++++++++++++
>  drivers/clk/rockchip/clk-rk3368.c             |  2 +-
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 20 +++++
>  drivers/gpu/drm/rockchip/rockchip_vop_reg.c   |  1 +
>  include/dt-bindings/clock/rk3368-cru.h        |  1 +
>  5 files changed, 102 insertions(+), 1 deletion(-)
> 
> --
> 2.47.2
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/next-20250829 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/rockchip/' for 20250831104855.45883-1-cn.liweihao@gmail.com:

arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[10, 129], [10, 371], [10, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-r88.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[10, 129], [10, 371], [10, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[10, 129], [10, 371], [10, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[11, 129], [11, 371], [11, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[10, 129], [10, 371], [10, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[10, 129], [10, 371], [10, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: vop@ff930000 (rockchip,rk3368-vop): 'reg-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): $nodename:0: 'mipi-dsi@ff960000' does not match '^dsi(@.*)?$'
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: mipi-dsi@ff960000 (rockchip,rk3368-mipi-dsi): compatible:0: 'rockchip,rk3368-mipi-dsi' is not one of ['rockchip,px30-mipi-dsi', 'rockchip,rk3128-mipi-dsi', 'rockchip,rk3288-mipi-dsi', 'rockchip,rk3399-mipi-dsi', 'rockchip,rk3568-mipi-dsi', 'rockchip,rv1126-mipi-dsi']
	from schema $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: /mipi-dsi@ff960000: failed to match any schema with compatible: ['rockchip,rk3368-mipi-dsi', 'snps,dw-mipi-dsi']
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): '#clock-cells' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clock-names: ['ref', 'pclk', 'pclk_host'] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): clocks: [[11, 129], [11, 371], [11, 356]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dtb: video-phy@ff968000 (rockchip,rk3368-dsi-dphy): reg: [[0, 4288053248, 0, 16384], [0, 4288020480, 0, 16384]] is too long
	from schema $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#

Re: (subset) [PATCH v1 0/7] drm/rockchip: Add MIPI DSI support for RK3368

[Heiko Stuebner]

On Sun, 31 Aug 2025 18:48:48 +0800, WeiHao Li wrote:
> This series adds MIPI DSI support for the Rockchip RK3368 SoC, enabling
> native display connectivity through the MIPI DSI host controller and
> PHY. The changes span multiple subsystems, including clock control,
> DRM/VOP integration, DSI controller binding, and PHY driver updates.
> 
> Key changes:
>   - Update the Rockchip MIPI DSI PHY driver to preperly handle RK3368
>     phy initialization.
>   - Add missing lut_size of vop_data for RK3368.
>   - Add missing clock ID SCLK_MIPIDSI_24M to the RK3368 CRU driver,
>     which is required for enabling the 24MHz reference clock.
>   - Add MIPI DSI node to rk3368.dtsi with correct clocks, resets,
>     and register mappings.
> 
> [...]

Applied, thanks!

[3/7] dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
      commit: 4a76a0a889cef284327f265f97edc4ff2f3e11cc
[4/7] clk: rockchip: use clock ids for SCLK_MIPIDSI_24M on rk3368
      commit: 77111b2c22ef5b368da5c833175b6f7806b39ccb

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>