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Fri, 16 Oct 2020 13:40:09 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 98F15C433F1; Fri, 16 Oct 2020 13:40:08 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id CB91CC433CB; Fri, 16 Oct 2020 13:40:07 +0000 (UTC) MIME-Version: 1.0 Date: Fri, 16 Oct 2020 19:10:07 +0530 From: Sai Prakash Ranjan To: Suzuki Poulose Subject: Re: [PATCH] coresight: etm4x: Skip setting LPOVERRIDE bit for qcom,skip-power-up In-Reply-To: <9e19d312-9de4-2ed8-75ca-c774b93bfe11@arm.com> References: <20201016101025.26505-1-saiprakash.ranjan@codeaurora.org> <5c4f6f5d-b07d-0816-331f-7c7463fa99b3@arm.com> <41bbcd43c2b016b6d785c3750622e9fe@codeaurora.org> <9e19d312-9de4-2ed8-75ca-c774b93bfe11@arm.com> Message-ID: <85ade254494144efc20c8c7512828654@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201016_094022_604007_8C6B5CED X-CRM114-Status: GOOD ( 20.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: denik@chromium.org, Mathieu Poirier , linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Suzuki, On 2020-10-16 18:45, Suzuki Poulose wrote: > On 10/16/20 12:47 PM, Sai Prakash Ranjan wrote: >> Hi Suzuki, >> >> On 2020-10-16 16:51, Suzuki Poulose wrote: >>> Hi Sai, >>> >>> On 10/16/20 11:10 AM, Sai Prakash Ranjan wrote: >>>> There is a bug on the systems supporting to skip power up >>>> (qcom,skip-power-up) where setting LPOVERRIDE bit(low-power >>>> state override behaviour) will result in CPU hangs/lockups >>>> even on the implementations which supports it. So skip >>>> setting the LPOVERRIDE bit for such platforms. >>>> >>>> Fixes: 02510a5aa78d ("coresight: etm4x: Add support to skip trace >>>> unit power up") >>>> Signed-off-by: Sai Prakash Ranjan >>> >>> The fix is fine by me. Btw, is there a hardware Erratum assigned for >>> this ? It would be good to have the Erratum documented somewhere, >>> preferrably ( Documentation/arm64/silicon-errata.rst ) >>> >> >> No, afaik we don't have any erratum assigned to this bug. > > Ok. Please double check, if there are any. > Sure I will check again. >> It was already present in downstream kernel and since we >> support these targets with the previous HW bug >> (qcom,skip-power-up) now in upstream, we would need this >> fix in upstream kernel as well. > > I understand the need for the fix and we must fix it. I was > looking to document this in the central place for errata's > handled in the kernel. And I missed asking this question > when the original patch was posted. So, thought of asking > the question now anyways. Better late than never ;-) > > Reviewed-by: Suzuki K Poulose Thanks. One more thing, does the internal erratum number (if it exists) is good enough to be documented in the Documentation/arm64/silicon-errata.rst ? I ask this because outside qualcomm, it won't mean much right. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel