From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B3FCC433DB for ; Thu, 31 Dec 2020 12:23:41 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 25429223DB for ; Thu, 31 Dec 2020 12:23:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 25429223DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SECPu/gBWJ7AoPxbDnHVIKCNs7dJcqre7QVu7Ca6RF8=; b=lhQdg+V4GcqmVcl/O/61Oj3i4 8sKWi6Lt3I20LukQrRtqtrC3yT7D6krv4H45rYRORZOaatouZaDOBLOHlhAqpvbj7uQNN2qTcMpGK ZjKbK64XhwCllb4YGlWkT7h+9Tmz+qv+gZfinBCSyG0lY1oE4gI4v7zMV9O7yfoMblovrE2bA+cMt xtjJte2xzfUX+KfJ9Ur3mJsVa7mR+5CCkWzB2XP544LArApk4XUYQXQGtwxoiVJIOOu9KdwMlXTED Ia/OZxxZJLsljEpetShgzGjB1K8K8oBoO2iVqZlgZxResXZMpwmtWJTFqQY9/Eu39iZ4RLFNZZoHe KvJfJxI3w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kuwyD-0003aY-C7; Thu, 31 Dec 2020 12:22:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kuwy8-0003Yo-9c for linux-arm-kernel@lists.infradead.org; Thu, 31 Dec 2020 12:22:17 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0E7FB223DB; Thu, 31 Dec 2020 12:22:15 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kuwy4-004iEa-Tk; Thu, 31 Dec 2020 12:22:12 +0000 MIME-Version: 1.0 Date: Thu, 31 Dec 2020 12:22:12 +0000 From: Marc Zyngier To: Shenming Lu Subject: Re: [PATCH RFC] KVM: arm64: vgic: Decouple the check of the EnableLPIs bit from the ITS LPI translation In-Reply-To: References: <20201231062813.714-1-lushenming@huawei.com> <683134bdea8a22d3bb784117dcfe17a1@kernel.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <85dd45f580eaa7a0b8ec91ac0b7ca066@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: lushenming@huawei.com, will@kernel.org, eric.auger@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, wanghaibin.wang@huawei.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201231_072216_518206_5A3FEBC0 X-CRM114-Status: GOOD ( 22.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Eric Auger , yuzenghui@huawei.com, wanghaibin.wang@huawei.com, Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-12-31 11:58, Shenming Lu wrote: > On 2020/12/31 16:57, Marc Zyngier wrote: >> Hi Shemming, >> >> On 2020-12-31 06:28, Shenming Lu wrote: >>> When the EnableLPIs bit is set to 0, any ITS LPI requests in the >>> Redistributor would be ignored. And this check is independent from >>> the ITS LPI translation. So it might be better to move the check >>> of the EnableLPIs bit out of the LPI resolving, and also add it >>> to the path that uses the translation cache. >> >> But by doing that, you are moving the overhead of checking for >> EnableLPIs from the slow path (translation walk) to the fast >> path (cache hit), which seems counter-productive. > > Oh, I didn't notice the overhead of the checking, I thought it would > be negligible... It probably doesn't show on a modern box, but some of the slower systems might see it. Overall, this is a design decision to keep the translation cache as simple and straightforward as possible: if anything affects the output of the cache, we invalidate it, and that's it. > >> >>> Besides it seems that >>> by this the invalidating of the translation cache caused by the LPI >>> disabling is unnecessary. >>> >>> Not sure if I have missed something... Thanks. >> >> I am certainly missing the purpose of this patch. >> >> The effect of EnableLPIs being zero is to drop the result of any >> translation (a new pending bit) on the floor. Given that, it is >> immaterial whether this causes a new translation or hits in the >> cache, as the result is still to not pend a new interrupt. >> >> I get the feeling that you are trying to optimise for the unusual >> case where EnableLPIs is 0 *and* you have a screaming device >> injecting tons of interrupt. If that is the case, I don't think >> this is worth it. > > In fact, I just found (imagining) that if the EnableLPIs bit is 0, > the kvm_vgic_v4_set_forwarding() would fail when performing the LPI > translation, but indeed we don't try to pend any interrupts there... > > By the way, it seems that the LPI disabling would not affect the > injection of VLPIs... Yes, good point. We could unmap the VPE from all ITS, which would result in all translations to be discarded, but this has the really bad side effect of *also* preventing the delivery of vSGIs, which isn't what you'd expect. Overall, I don't think there is a good way to support this, and maybe we should just prevent EnableLPIs to be turned off when using direct injection. After all, the architecture does allow that for GICv3 implementations, which is what we emulate. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel