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Thu, 9 Apr 2020 01:00:01 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 9 Apr 2020 01:00:01 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 9 Apr 2020 01:00:01 -0500 Received: from [10.24.69.20] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0395xvDZ048578; Thu, 9 Apr 2020 00:59:58 -0500 Subject: Re: [PATCH] irqchip/ti-sci-inta: fix processing of masked irqs To: Grygorii Strashko , Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Jason Cooper , Marc Zyngier References: <20200408191532.31252-1-grygorii.strashko@ti.com> From: Lokesh Vutla Message-ID: <85de7f21-2e9b-da16-589e-b4c2144f3ab4@ti.com> Date: Thu, 9 Apr 2020 11:29:56 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20200408191532.31252-1-grygorii.strashko@ti.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200408_230017_216150_88F6B6BE X-CRM114-Status: GOOD ( 11.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Ujfalusi , Sekhar Nori , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vignesh Raghavendra Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/04/20 12:45 AM, Grygorii Strashko wrote: > The ti_sci_inta_irq_handler() does not take into account INTA IRQs state > (masked/unmasked) as it uses INTA_STATUS_CLEAR_j register to get INTA IRQs > status, which provides raw status value. > This causes hard IRQ handlers to be called or threaded handlers to be > scheduled many times even if corresponding INTA IRQ is masked. > Above, first of all, affects the LEVEL interrupts processing and causes > unexpected behavior up the system stack or crash. > > Fix it by using the Interrupt Masked Status INTA_STATUSM_j register which > provides masked INTA IRQs status. > > Fixes: 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") > Signed-off-by: Grygorii Strashko Reviewed-by: Lokesh Vutla Thanks and regards, Lokesh _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel