From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D12BBC3DA49 for ; Fri, 26 Jul 2024 08:32:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:References:Cc:To:Subject:From:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9t4humPsegdXf5hJllpZAZGKu8XIkSJq0aEJAmehh3I=; b=eODApeWNlBl7tR7C7innNsALDS lMneRon0/cdjsE7Ba2stgTaaAlQmyI6iHtthmpeP1Wd7hM1jZMZs2NZLqb99uKytC5W0TlRLMxzii K+EtWGvkyKn9zK7JmB0e6diovXqajYBLn0s3JlxPYD1Y3e6OISeK+k5wfo+vNs5qfrbYQ8yZ+fcON Fv1oMGTKh4NPoJrZq9x9ccBuLv8BeuMJ84YFkpBR1n0Fcb0Au3ohVIYF5Frziv4R5rl5UxMqJHfcu mcHMln/A6VE7aO6yKOeoZgOw2cCKFQyjXQ9tq5ywOuotTnSFC+DK7pxENuLR6yEbOcsi+aGjuyxST Mzkdpb/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXGNA-00000003Kai-1zqm; Fri, 26 Jul 2024 08:32:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXGMm-00000003KWI-26F0 for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2024 08:31:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5920E1007; Fri, 26 Jul 2024 01:32:19 -0700 (PDT) Received: from [10.163.53.239] (unknown [10.163.53.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CAA033F5A1; Fri, 26 Jul 2024 01:31:52 -0700 (PDT) Message-ID: <85e9b2ce-775a-4183-91e3-65b8eec0bdad@arm.com> Date: Fri, 26 Jul 2024 14:01:49 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Anshuman Khandual Subject: Re: [boot-wrapper 3/3] aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org References: <20240723110630.483871-1-anshuman.khandual@arm.com> <20240723110630.483871-4-anshuman.khandual@arm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240726_013156_609005_27CDBBBF X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/25/24 14:21, Mark Rutland wrote: > On Tue, Jul 23, 2024 at 04:36:30PM +0530, Anshuman Khandual wrote: >> FEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system >> registers from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set. >> >> Enable access to RCW[S]MASK_EL1 registers when they are implemented. > > This looks fine. > > IIUC we don't need to initialize these new registers as they only affect > the behaviour of new instructions which we don't expect SW to use until > privileged SW has configured these registers (as they reset to UNKNOWN > values even at the highest implemented EL). Right, will keep patch's position in the series unchanged as well. > > Mark. > >> Signed-off-by: Anshuman Khandual >> --- >> arch/aarch64/include/asm/cpu.h | 2 ++ >> arch/aarch64/init.c | 3 +++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h >> index 57d66e4..8404152 100644 >> --- a/arch/aarch64/include/asm/cpu.h >> +++ b/arch/aarch64/include/asm/cpu.h >> @@ -55,6 +55,7 @@ >> #define SCR_EL3_TME BIT(34) >> #define SCR_EL3_HXEn BIT(38) >> #define SCR_EL3_EnTP2 BIT(41) >> +#define SCR_EL3_RCWMASKEn BIT(42) >> #define SCR_EL3_TCR2EN BIT(43) >> #define SCR_EL3_SCTLR2En BIT(44) >> #define SCR_EL3_PIEN BIT(45) >> @@ -92,6 +93,7 @@ >> >> #define ID_AA64PFR1_EL1_MTE BITS(11, 8) >> #define ID_AA64PFR1_EL1_SME BITS(27, 24) >> +#define ID_AA64PFR1_EL1_THE BITS(51, 48) >> #define ID_AA64PFR0_EL1_SVE BITS(35, 32) >> >> #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 >> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c >> index 5b21cb8..13a2339 100644 >> --- a/arch/aarch64/init.c >> +++ b/arch/aarch64/init.c >> @@ -95,6 +95,9 @@ void cpu_init_el3(void) >> if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) >> scr |= SCR_EL3_SCTLR2En; >> >> + if (mrs_field(ID_AA64PFR1_EL1, THE)) >> + scr |= SCR_EL3_RCWMASKEn; >> + >> msr(SCR_EL3, scr); >> >> msr(CPTR_EL3, cptr); >> -- >> 2.25.1 >>