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From: Marc Zyngier <maz@kernel.org>
To: Yize Wang <wangyize7@huawei.com>
Cc: <kvmarm@lists.linux.dev>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <catalin.marinas@arm.com>,
	<will@kernel.org>, <fuad.tabba@linux.dev>, <joey.gouly@arm.com>,
	<seiden@linux.ibm.com>, <suzuki.poulose@arm.com>,
	<yuzenghui@huawei.com>, <mark.rutland@arm.com>,
	<zhengchuan@huawei.com>, <jiangjiacheng@huawei.com>,
	<yize_w1110@163.com>
Subject: Re: [RESEND][PATCH 0/2] Batch register access for live migration optimization
Date: Mon, 12 Oct 2026 12:31:17 +0100	[thread overview]
Message-ID: <861p9v2m0q.wl-maz@kernel.org> (raw)
In-Reply-To: <6890def8-168d-4951-b6bd-bcbbcbf3595a@huawei.com>

On Thu, 08 Oct 2026 13:50:57 +0100,
Yize Wang <wangyize7@huawei.com> wrote:
> 
> 
> 在 2026/10/3 22:53, Marc Zyngier 写道:
> > On Sun, 20 Sep 2026 10:15:25 +0100,
> > Yize Wang <wangyize7@huawei.com> wrote:
> >> 在 2026/9/18 20:08, Marc Zyngier 写道:
> >>> On Fri, 18 Sep 2026 09:18:13 +0100,
> >>> Yize Wang<wangyize7@huawei.com> wrote:
> >>    These patches focus on optimizing GICv3 register access during live
> >> migration. We found that there are a large number of locks (kvm->lock,
> >> vcpus, config_lock) in the GIC, these lock operations wil cost large
> >> time waste. The batches of sysreg for vcpu optimization will come in
> >> follow as a separate series. And let me address these questions one by
> >> one.
> > All these locks should be non-blocking by the time you save anything
> > related to the GIC, because:
> > 
> > - none of the vcpu can be running
> > 
> > - this must be a single threaded operation
> > 
> > So if you are seeing anything contended, this is either the sign of a
> > bad KVM bug, or an indication that you are violating the above
> > requirements.
> > 
> > 	M.
> 
> 
> Hi, Marc! Thanks for your review.
> 
> You are right that when saving the GIC state during live migration
> process, all vCPUs are not running and it is a single threaded
> operation. Our patches process the packaged register states from the
> userspace under the same lock. These operations only aim to reduce
> the lock opreation downtime and do not involve lock contention.

OK, so your argument was actively misleading, since you were claiming
that locks were the majority of the overhead, and are now
advocating... something else.

> In addition, these patches focus on reducing the syscalls of
> ioctl. Now, every register requires an ioctl, resulting in (num_cpu
> * registers_per_cpu) system calls. This will cost lots of time
> during the large-scale VM migration. Our patches batch registers by
> category in qemu and then send them to kernel in batches. This
> operations significantly reduce the number of ioctl syscalls and
> save a great amount of downtime.

I've suggested you use io_uring, and you completely disregarded my
suggestion based on... locking contention. How do you expect me to
take you seriously?

I've now marked this series as rejected. Please come back once you and
your AI toy have agreed on what you want to do.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.


      parent reply	other threads:[~2026-10-12 11:31 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-18  8:18 [PATCH 0/2] Batch register access for live migration optimization Yize Wang
2026-09-18  8:18 ` [PATCH 1/2] KVM: arm64: Add batch group constant and data structure to UAPI header Yize Wang
2026-09-18  8:18 ` [PATCH 2/2] KVM: arm64: Add VGIC v3 batch register access implementation Yize Wang
2026-09-18 12:08 ` [PATCH 0/2] Batch register access for live migration optimization Marc Zyngier
2026-09-20 12:12   ` [RESEND][PATCH " Yize Wang
2026-09-23  7:57     ` Yize Wang
     [not found]   ` <f70c6fe3-e3c5-4912-b4bb-8a418fec4346@huawei.com>
2026-10-03 14:53     ` [PATCH " Marc Zyngier
2026-10-08  8:32       ` Yize Wang
2026-10-08 12:50       ` [RESEND][PATCH " Yize Wang
2026-10-12 11:04         ` Yize Wang
2026-10-12 11:31         ` Marc Zyngier [this message]

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