From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00464FF885D for ; Sun, 26 Apr 2026 09:14:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wDoxXpnYNkI9G++A3DymN5g3Rtb6cBmbOTHxfQDWeAk=; b=FpkfimqRE/BILyIKVCg/4st7lA Tttda9pJbKrktdOpK+VGs6mi5GZljbcMcn77FsHpi29QKuFLoGfB5jGmnoJeVeU/6KGs7IP0e9i6o 42vxdOqpDMABz4cZqkySPPiSB9HUUTPDge2VU9o5LmbVd8LkbF1KxgCs0M1f95Pk6AcjQYU0nFzqN AgjV33dFNJec+Wdqst5ce0pMZQKlGHg3dFfKCmL62tPKEAAoOsXD9HoUoc5CR+YZby14wv2ygpGQp 99XLvNPjFB8fTS0jwxzXQXOQ9my3Am+WEiUOfmc6WLsoijdLXPeSU+cnON0mLmbldLEHDJNfvrcD0 uLCp3WNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wGvZC-0000000FOBG-1asI; Sun, 26 Apr 2026 09:14:18 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1wGvZA-0000000FOAx-2dG8 for linux-arm-kernel@lists.infradead.org; Sun, 26 Apr 2026 09:14:16 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id B10A4600AE; Sun, 26 Apr 2026 09:14:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5EECDC2BCAF; Sun, 26 Apr 2026 09:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777194854; bh=mIDtI2DvRmR2rKhKS/QpZYOxXcixSL38uwNQkFExpJY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=sKiWiQjHfFPALfrhENoLfMQrcqClLCseJNaGBJlhSiIKV/HVCJLNeNJH0yA5F0wJl uDOLlNPKzqwTfmvWOZyu4BhSzTRr+e64lOVw5Qlz/U/La4Xe4IXrJTHRAp3m1hKe0O eGo4hI+2rsda6kMdHrpRYRstWmUiSyWJYffq4JXhHs7C+ynRQwYti1gxXLk7RDW7YL q2Ty/Z7nD44BnBAyp2L24hV7ZV7YXX++j8ERtT8ugq1VtT6ol4AmkavnX1oo6kbeaT /CIgLGoufUknVpBI35ZF8EPuHTn86aDaTf1LH/rVvfzG21CTD1voMqJaaPnRZcrijv mq+UTY6/DzDRA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wGvZ5-0000000EkyH-46jc; Sun, 26 Apr 2026 09:14:12 +0000 Date: Sun, 26 Apr 2026 10:14:11 +0100 Message-ID: <861pg213to.wl-maz@kernel.org> From: Marc Zyngier To: Vishnu Pajjuri Cc: Fuad Tabba , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Christoffer Dall , Mark Brown , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Darren Hart Subject: Re: [PATCH v4 35/49] KVM: arm64: GICv3: nv: Plug L1 LR sync into deactivation primitive In-Reply-To: References: <20251120172540.2267180-1-maz@kernel.org> <20251120172540.2267180-36-maz@kernel.org> <2e12c5c2-a1b6-47b7-b54c-7281a77bbe0a@os.amperecomputing.com> <878qb9cxzr.wl-maz@kernel.org> <1e050b67-2276-41ad-9265-796ba853dc7c@os.amperecomputing.com> <86a4vo49ni.wl-maz@kernel.org> <86eck71o1v.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: vishnu@os.amperecomputing.com, tabba@google.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, christoffer.dall@arm.com, broonie@kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, darren@os.amperecomputing.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 22 Apr 2026 15:57:44 +0100, Vishnu Pajjuri wrote: > > Hi Marc, > > On 22-04-2026 12:25, Marc Zyngier wrote: > > > > Have you made progress on this? I can't reproduce it at all despite my > > best effort. I'm perfectly happy to help, but you need to give me > > *something* to go on. > > > Thanks for your support!! > > The issue is triggered as soon as the timer interrupt (IRQ 27) is > deactivated. Preventing the deactivation of IRQ 27 during nested VGIC > state transitions prevents the failure from reproducing. Which level of deactivation? From L2 to L1? Or L1 to L0? The former should just be a an update to the irq structure, while the latter is effectively a write to ICC_DIR_EL1, and *that* is a new behaviour introduced by this patch. I wonder if your implementation is such that ICC_DIR_EL1 is trapped by ICH_HCR_EL2.TDIR, which is allowed by the architecture, but that none of the two implementations I have actually enforce (the trap only applies to ICV_DIR_EL1). Can you try the hack below which disables the traps much earlier, and let me know if that helps? Even if that's the case, this should result in an EL2->EL2 exception, and that should be caught as an unhandled exception in entry-common.c, so something else is afoot. Thanks, M. diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c index 5c69fa615823c..ee415c1038b4e 100644 --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c @@ -280,6 +280,14 @@ void vgic_v3_sync_nested(struct kvm_vcpu *vcpu) struct shadow_if *shadow_if = get_shadow_if(); int i; + /* We need these to be synchronised to generate the MI */ + __vcpu_assign_sys_reg(vcpu, ICH_VMCR_EL2, read_sysreg_s(SYS_ICH_VMCR_EL2)); + __vcpu_rmw_sys_reg(vcpu, ICH_HCR_EL2, &=, ~ICH_HCR_EL2_EOIcount); + __vcpu_rmw_sys_reg(vcpu, ICH_HCR_EL2, |=, read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_EOIcount); + + write_sysreg_s(0, SYS_ICH_HCR_EL2); + isb(); + for_each_set_bit(i, &shadow_if->lr_map, kvm_vgic_global_state.nr_lr) { u64 val, host_lr, lr; @@ -309,14 +317,6 @@ void vgic_v3_sync_nested(struct kvm_vcpu *vcpu) vgic_v3_deactivate(vcpu, FIELD_GET(ICH_LR_PHYS_ID_MASK, lr)); } - /* We need these to be synchronised to generate the MI */ - __vcpu_assign_sys_reg(vcpu, ICH_VMCR_EL2, read_sysreg_s(SYS_ICH_VMCR_EL2)); - __vcpu_rmw_sys_reg(vcpu, ICH_HCR_EL2, &=, ~ICH_HCR_EL2_EOIcount); - __vcpu_rmw_sys_reg(vcpu, ICH_HCR_EL2, |=, read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_EOIcount); - - write_sysreg_s(0, SYS_ICH_HCR_EL2); - isb(); - vgic_v3_nested_update_mi(vcpu); } -- Without deviation from the norm, progress is not possible.