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Fri, 01 Mar 2024 19:14:01 +0000 Date: Fri, 01 Mar 2024 19:14:00 +0000 Message-ID: <861q8t3guf.wl-maz@kernel.org> From: Marc Zyngier To: Joey Gouly Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon , Catalin Marinas Subject: Re: [PATCH v2 07/13] KVM: arm64: nv: Honor HFGITR_EL2.ERET being set In-Reply-To: <20240301180734.GA3958355@e124191.cambridge.arm.com> References: <20240226100601.2379693-1-maz@kernel.org> <20240226100601.2379693-8-maz@kernel.org> <20240301180734.GA3958355@e124191.cambridge.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: joey.gouly@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240301_111407_394876_094DC9DA X-CRM114-Status: GOOD ( 34.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Joey, On Fri, 01 Mar 2024 18:07:34 +0000, Joey Gouly wrote: > > Got a question about this one, > > On Mon, Feb 26, 2024 at 10:05:55AM +0000, Marc Zyngier wrote: > > If the L1 hypervisor decides to trap ERETs while running L2, > > make sure we don't try to emulate it, just like we wouldn't > > if it had its NV bit set. > > > > The exception will be reinjected from the core handler. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/hyp/vhe/switch.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c > > index eaf242b8e0cf..3ea9bdf6b555 100644 > > --- a/arch/arm64/kvm/hyp/vhe/switch.c > > +++ b/arch/arm64/kvm/hyp/vhe/switch.c > > @@ -220,7 +220,8 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code) > > * Unless the trap has to be forwarded further down the line, > > * of course... > > */ > > - if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) > > + if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) || > > + (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET)) > > return false; > > > > spsr = read_sysreg_el1(SYS_SPSR); > > Are we missing a forward_traps() call in kvm_emulated_nested_eret() for the > HFGITR case? > > Trying to follow the code path here, and I'm unsure of where else the > HFIGTR_EL2_ERET trap would be forwarded: > > kvm_arm_vcpu_enter_exit -> > ERET executes in guest > fixup_guest_exit -> > kvm_hyp_handle_eret (returns false) > > handle_exit -> > kvm_handle_eret -> > kvm_emulated_nested_eret > if HCR_NV > forward traps > else > emulate ERET There's a bit more happening in kvm_handle_eret(). > > > And if the answer is that it is being reinjected somewhere, putting that > function name in the commit instead of 'core handler' would help with > understanding! Let's look at the code: static int kvm_handle_eret(struct kvm_vcpu *vcpu) { [...] if (is_hyp_ctxt(vcpu)) kvm_emulate_nested_eret(vcpu); If we're doing an ERET from guest EL2, then we just emulate it, because there is nothing else to do. Crucially, HFGITR_EL2.ERET doesn't apply to EL2. else kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); In any other case, we simply reinject the trap into the guest EL2, because that's the only possible outcome. And that's what you were missing. return 1; } > I need to find the time to get an NV setup set-up, so I can do some experiments > myself. The FVP should be a good enough environment if you can bare the glacial speed. Other than that, I hear that QEMU has grown some NV support lately, but I haven't tried it yet. HW-wise, M2 is the only machine that can be bought by a human being (everything else is vapourware, or they would have already taken my money). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel